So i am designing this analog circuit, basically which can delay a singal (ac signal) by about 1ms. I am looking into the bucket brigade concept as invented by F.L.J.Sansgter back in the 1960s and 70s.
The circuit and basic topology can be found on these web pages:
(2.1 from here)
Basically, you have a row of Nmos or Pmos transistors turning on and off with two out of phase clock pulses at their gate. The source/drain is connected to a capacitor which stores the charges. So after a number of such stages, the signal gets delayed.
However, i am having trouble with Cadence simulating it. I have tried LTspice and Multisim, which show the simulation as a delay, but Cadence does not. This is important as for my custom IC i have to simulate and get it working in Cadence first and then do the LVS as well.
I am attaching the images from my design and simulation run.
I am using VPulse to generate the clocks.
I am using Vsin to generate a sine wave. The signal can be arbitrary as right now the aim is to get some sort of delay.
Transistors are the standard NMOS from the XH035 PRIMLIB family, as we are going to run for 350nm process.
The capacitors, resistors and ground are from the analogLib.
I have put in a filter at the end and on the simulation you can see the signal out with and without the filter.
Please help me analyze this. The weird thing is that it seems to be working in LTspice but not in Cadence. I have tried adding a source-follower at the signal out, but it still doesn't help.
Is there anything special i need to do?
Oh yes, i am using Cadence Virtuoso IC184.108.40.2060.13
Thank you for your prompt replies, Andrew.
What i meant about real time capacitance was that do i need to do something with RCx to let Virtuoso know that it is simulation for real time?
What size of buckets do you recommend? I have tried picofarads but to no avail.
Also, the signal can be all in +ve region using DC offset, so that's not an issue. All i want is to see some sort of delay