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Doubt regarding layout gpdk 45nm

madhusudha

Hello

I am are doing my UG Final year project using cadence gpdk 45nm technology,

It would be of great help if someone explain and help us find a solution for the following two error messages:

  => OXIDE.A.1:Minimum area for Active area >=0.035 um

  =>METAL.A.1:Metal area must be >=0.02 um

These errors pertain to vias used- nwell and psub

Could someone also brief about the vias used  for nmos and pmos in gpdk 45nm technology?

Thanks in advance!

Parents
  • Andrew Beckett

    Well, the metal area shouldn't be an issue because you'd want to route to them, presumably.

    Similarly you'd usually ensure that the oxide (diffusion) is large enough - you can do this either by placing the via connected to an oxide region, or place a multiple via (set the rows or columns to 3 - this sets the area big enough that a standalone via would not cause an issue, but in practice you're going to want to connect it to something!).

    I don't understand your last question.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    Well, the metal area shouldn't be an issue because you'd want to route to them, presumably.

    Similarly you'd usually ensure that the oxide (diffusion) is large enough - you can do this either by placing the via connected to an oxide region, or place a multiple via (set the rows or columns to 3 - this sets the area big enough that a standalone via would not cause an issue, but in practice you're going to want to connect it to something!).

    I don't understand your last question.

    Regards,

    Andrew.

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