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  3. Problem in Cadence Virtuoso AC analysis

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Problem in Cadence Virtuoso AC analysis

OneNewBoy
OneNewBoy over 12 years ago

Hi all,

I am facing an often discussed problem  while simulating a differential pair in cadence virtuoso.

Though I have biased the transistors through DC  (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic is attached.

Can someone help me in debugging this ?

 

 

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  • Andrew Beckett
    Andrew Beckett over 12 years ago

    My guess is that there's either something wrong with your models, or that the dimensions passed in are wrong. For example, your L is 20nm, but the W is 7 metres!

    I did some adjustment (I don't have your models, so I made some up), and it's simulating OK for me:

     // Generated for: spectre
    // Generated on: Mar 22 14:37:53 2013
    // Design library name: Basic_Blocks
    // Design cell name: DiffAmp_MOS
    // Design view name: schematic
    simulator lang=spectre
    global 0 vdd!
    parameters C=2p Ibias=1u Vac=0.1 VDD=0.4 VinNDC=0.2 VinPDC=0.2 Wnl=7 Wpl=7
     
    // very simple models because I don't have your models...
    inline subckt SubNMOS_noisy (d g s)
     parameters W=1 L=1
     SubNMOS_noisy (d g s 0) nch w=W*1u l=L*10
     model nch bsim4 type=n
    ends SubNMOS_noisy

    inline subckt SubPMOS_noisy (d g s)
     parameters W=1 L=1
     SubPMOS_noisy (d g s s) pch w=W*1u l=L*10
     model pch bsim4 type=p
    ends SubPMOS_noisy

    // Library name: Basic_Blocks
    // Cell name: DiffAmp_MOS
    // View name: schematic
    I2 (net2 0) isource dc=Ibias type=dc
    V2 (VinN 0) vsource dc=VinNDC type=dc
    V3 (net012 0) vsource dc=VinPDC type=dc
    V0 (vdd! 0) vsource dc=VDD type=dc
    C0 (Vout 0) capacitor c=C
    Vac (VinP net012) vsource dc=0 mag=Vac phase=0 type=sine sinedc=0 ampl=Vac \
            sinephase=0 freq=1K
    I21 (net3 net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I20 (Vout net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I23 (Vout VinN net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    I22 (net3 VinP net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    ac ac start=1 stop=1G dec=20 save=all annotate=status
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub currents=all
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubPMOS_noisy/veriloga/veriloga.va"
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubNMOS_noisy/veriloga/veriloga.va"

    (I fiddled with the lengths, because  I got very little gain with the values you'd entered, but my models are completely artificial).

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 12 years ago

    My guess is that there's either something wrong with your models, or that the dimensions passed in are wrong. For example, your L is 20nm, but the W is 7 metres!

    I did some adjustment (I don't have your models, so I made some up), and it's simulating OK for me:

     // Generated for: spectre
    // Generated on: Mar 22 14:37:53 2013
    // Design library name: Basic_Blocks
    // Design cell name: DiffAmp_MOS
    // Design view name: schematic
    simulator lang=spectre
    global 0 vdd!
    parameters C=2p Ibias=1u Vac=0.1 VDD=0.4 VinNDC=0.2 VinPDC=0.2 Wnl=7 Wpl=7
     
    // very simple models because I don't have your models...
    inline subckt SubNMOS_noisy (d g s)
     parameters W=1 L=1
     SubNMOS_noisy (d g s 0) nch w=W*1u l=L*10
     model nch bsim4 type=n
    ends SubNMOS_noisy

    inline subckt SubPMOS_noisy (d g s)
     parameters W=1 L=1
     SubPMOS_noisy (d g s s) pch w=W*1u l=L*10
     model pch bsim4 type=p
    ends SubPMOS_noisy

    // Library name: Basic_Blocks
    // Cell name: DiffAmp_MOS
    // View name: schematic
    I2 (net2 0) isource dc=Ibias type=dc
    V2 (VinN 0) vsource dc=VinNDC type=dc
    V3 (net012 0) vsource dc=VinPDC type=dc
    V0 (vdd! 0) vsource dc=VDD type=dc
    C0 (Vout 0) capacitor c=C
    Vac (VinP net012) vsource dc=0 mag=Vac phase=0 type=sine sinedc=0 ampl=Vac \
            sinephase=0 freq=1K
    I21 (net3 net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I20 (Vout net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I23 (Vout VinN net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    I22 (net3 VinP net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    ac ac start=1 stop=1G dec=20 save=all annotate=status
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub currents=all
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubPMOS_noisy/veriloga/veriloga.va"
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubNMOS_noisy/veriloga/veriloga.va"

    (I fiddled with the lengths, because  I got very little gain with the values you'd entered, but my models are completely artificial).

    Regards,

    Andrew.

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