• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. how do I tell VXL about a virtual connection?

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 15023
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

how do I tell VXL about a virtual connection?

linbo
linbo over 12 years ago

Is there a facility to virtually connect lines within VXL and have them stop showing up in Incomplete Nets in the Annotation Browser?

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 12 years ago

    The situation where you'd want to do this is presumably where the connection is going to be made outside of the cell - so you're wanting to define a "must connect". This only makes sense for pins of the block. 

    Imagine that you have one part of the "vdd" net, currently wired up to a pin called "vdd". Then you have another region of routing on the vdd net, currently not wired to a pin at all - but it's showing a flight line between the two.

    In order to add a "must connect", you have to have two separate terminals (in IC61, as the OpenAccess connectivity model is different than CDB) - so add a pin on the second region of routing and specify the terminal name as (say) "vdd_2". Then bring up Connectivity->Pins->Pin Connectivity Setting (unfortunately a rather confusing form, so much so that I wrote a solution on how to use it). Select the two terminals "vdd" and "vdd_2" and do Right Mouse->Make Must Connect Group. That should fix the annotation browser, because it now knows that these two regions of routing will be connected at a higher level.

    The reason why the two terminals need to have different names is because they really aren't connected inside the design - so it doesn't really make sense for them to be given the same name if you aren't going to connect them. If they are multiple pins within the same block, they'd naturally be "strong connected" - which means that you can route to either of them - or you can mark them as "weak connect" which means that you aren't allowed to use them as a feed through (e.g. the poly gate of a transistor).

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • linbo
    linbo over 12 years ago

    Wow, thanks Andrew. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information