I'm designing an oscillator with a quartz (Pierce model). The circuit is basically an amplifier and the quartz. I would like to measure the open loop gain and phase however I'm not sure about the method.
First method I tried is the following :
I disconnected the loop at the gate of the MOS amplifier inverter. Put a vac source and set the AC amplitude to 1V.I copied the schematic of the amplifier and pasted it at the output of the crystal, this way the crystal will see the same load as if it was in closed-loop. Then I measure the gain at the output of the crystal using a HB analysis.
Second method is :
I used the middlebrook analysis, which is stb in cadence. However I'm skeptical about this method as stb is to check the stability of the system. And, as I'm using an oscillator, I'm not supposed to be stable. However I'm still measuring an open loop gain and phase with stb analysis.
My question is which method is correct? I really have no idea on how to answer that question, so I'm here.
You are asking a number of questions that are really outside the scope of this forum I think - but I will let Andrew make that judgement. The questions are really appropriate for a forum on quartz oscillator design. Nevertheless, I will provide my insights since I do quartz oscillator design,
I'm not sure if my results are correct or not.
My result is -881Ohm at Fosc (40MHz), my gain is then equal to : 880/R1 (which is 21.58), 880/21.58 = 41.
My question is the following, I found on the internet that the result should be around 4-8 times the motional resistance R1, am I not a little too high?
How should I assess this result? What can I say about it?
I think that this result means that if I wanted my
oscillator to oscillate at 40MHz, I could do it because I have enough
gain. Am I correct?
Your basic calculation methodology for oscillator open loop gain is correct for the specific simulation you performed.
First, I do not know if you have considered what the minimum absolute value of negative resistance is over all process, supply voltage, and temperature conditions. I also noted that you appear to bias one transistor with an ideal voltage source. If you are trying to determine the minimum absolute value of negative resistance, you must examine all cases and exclude ideal bias elements. As mentioned above, I think if you use a more realistic value of C0, this will also significantly reduce the magnitude of your measured negative resistance at 40 MHz.
Second, there are many other considerations that one must weigh when choosing the proper value of negative resistance. A rule of thumb is not appropriate. For example, how does the negative resistance saturate as the amplitude of oscillation increases? How temperature and voltage sensitive is the negative resistance? How much quartz crystal resonator drive level sensitivity exists? How much frequency trim capacitance is required and how does that impact negative resistance? Hence, you need to answer these questions to determine how much margin is required for your circuit.
EDIT : My colleage asked me a question that I couldn't answer to. Why is the gain the ratio between the negative resistance and the motional resistance? Thank you.
I think my answer to this is outside the scope of this forum. Andrew, if you feel otherwise, I will respond.