Hi, I have a standard cell library in .v format. It contains different set of modules each defined under `ifdef. How can I import a specific set using verilogIn.? where can I set the value used for `ifdef?
Not sure if there's a better way (and I've not checked that even this will work), but one way could be to create a file, defines.v with:
`define THIS that`define OTHER whatever
i.e. `define the things you want found by the `ifdef. Then specify this file first in the list of Verilog files to import.
I'd be interested to know if it works (I don't have time to try it myself).
Thanks Andrew, it works.