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  3. noisefile in a vdc source modeled by Verilog-A

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noisefile in a vdc source modeled by Verilog-A

Aldo2
Aldo2 over 12 years ago

 Hello,

Is it possible to read a noise file from Verilog-A?

I would like to add a known noise shape to a model of a vdc voltage source modeled by Verilog-A.

(I need to read data from a file and pass them to noise_table)

thank you very much

Best regards

Aldo

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  • Andrew Beckett
    Andrew Beckett over 12 years ago

    Aldo,

    How about this code below. A simple command line testcase would be:

    // noise_from_file.scs

    I1 (n1) noise_from_file filename="noise.dat" //debug=1
    r1 (n1 0) resistor r=1k isnoisy=no

    ahdl_include "noise_from_file.va"

    noise (n1 0) noise start=1 stop=1G dec=10

    With this as the noise.dat:

    1e3,1e-9
    2e3,2e-9
    10e3,1.8e-9
    1e6,2.2e-9

     

    `include "disciplines.vams"
    
    module noise_from_file (op);
    
    output op;
    electrical op;
    integer mcd,count,retval;
    real frq,val;
    parameter string filename="noise.dat";
    parameter maxpoints=100;
    parameter debug=0;
    real noisetab[0:maxpoints-1];
    
    analog begin
    
       @(initial_step) begin
          mcd=$fopen(filename,"r");
          retval=2;
          count=0;
          while(retval==2) begin
    	  retval=$fscanf(mcd,"%f,%f",frq,val);
    	  if (debug) $debug("Data is %d %g %g",retval,frq,val);
    	  noisetab[count]=frq;
    	  count=count+1;
    	  noisetab[count]=val;
    	  count=count+1;
          end
          $fclose(mcd);
        end
    
        V(op) <+ noise_table(noisetab);
    end
    
    endmodule

     

    Regards,

    Andrew.

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  • Aldo2
    Aldo2 over 12 years ago

     Many thanks, Andrew

    Regards,

    Aldo

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  • Aldo2
    Aldo2 over 11 years ago

    Hi Andrew,

    Starting from your suggestions I wrote the following code:

    module TEST(VOUT,ADJ);
        inout      VOUT, ADJ;
        electrical VOUT, ADJ;

        integer    voutPar,file,i,retVal;
        real       vthr,noiseFrq,noiseVal,voutVal;
        string     filename,temp;
        real       noisetab[0:1000];

        analog begin
            vthr=0.1;
            if(V(ADJ)>vthr) voutPar=1;
            else voutPar=0;
            case (voutPar)
                0: begin
                       filename="TEST_1V.csv";
                       voutVal  =1;
                   end
                1: begin
                       filename="TEST_2V.csv";
                       voutVal  =2;
                   end
            endcase
            file=$fopen(filename,"r");
            $fscanf(file,"%s",temp);
            $display("%s",temp);
            i=0;
            retVal=$fscanf(file,"%f %f",noiseFrq,noiseVal);
            while(retVal==2) begin
                noisetab[i]=noiseFrq;
                i=i+1;
                noisetab[i]=noiseVal;
                i=i+1;
                retVal=$fscanf(file,"%f %f",noiseFrq,noiseVal);
            end
            $fclose(file);
            V(VOUT) <+ voutVal+noise_table(noisetab);
        end
    endmodule

     If voutPar=1, I get the following error message:

    Internal error found in spectre during DC analysis `dcOp'. 
    Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the Spectre log file, the behavioral model files, and any other information that can help identify the problem.
        FATAL (SPECTRE-18): Segmentation fault.

    Whereas if voutPar=0 it works.

    If I make load the same file in both cases:

    case (voutPar)
                    0: begin
                           filename="TEST_1V.csv";
                           voutVal  =1;
                       end
                    1: begin
                           filename="TEST_1V.csv";
                           voutVal  =2;
                       end
                endcase

    the code works

    Thank you

    Best regards

    Aldo

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