Stats

Locked Locked
Replies 2
Subscribers 126
Views 13784
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Need to place a pin on the symbol for an internal VerilogA signal

I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal.

So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic. But is it normal for internal signals to have pins on the symbol only because it will be passed to another module internally?

Thanks.

Parents

Andrew Beckett over 12 years ago

So how are you expecting to connect to this internal node? Normally connections would only be through the external connections of a module.
It's not obvious to me what you mean - maybe you can illustrate it with an example?
Kind Regards,
Andrew.
Cancel
Vote Up 0 Vote Down

Cancel

Reply

Andrew Beckett over 12 years ago

So how are you expecting to connect to this internal node? Normally connections would only be through the external connections of a module.
It's not obvious to me what you mean - maybe you can illustrate it with an example?
Kind Regards,
Andrew.
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.