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VHDL/Verilog simulation help in Virtuoso

Tejaswi
I am new to Virtuoso Cadence, and I am trying to create a Parallel to serial block using the Verilog or VHDL. I have written the VHDL code as well. The problem I'm getting is how to create the block.

This is how I have tried:

created the symbol, cell name to be paralleltoserial---->
From the cell view, edit>properties> VHDL----->
I have entered the Scalar and Vector data types----->
Here I got a Design> Create cell view > from cell view, and "to view name" is set to VHDL---->
Now a VHDL language editor is created. 

Here I have written my code: 

 entity PARALLELtoSERIAL is
        generic (N : POSITIVE := 8);
        port(PAR_DATA: in STD_LOGIC_VECTOR(1 to 8));
        CLK,DATA_READY : in STD_LOGIC;
        SER_OUT : out STD_LOGIC);
        end;
        
architecture SHIFT of PARALLELtoSERIAL is
        signal SAVE_REG : STD_LOGIC_VECTOR( 1 to N);
begin   
        process(CLK,DATA_READY,PAR_DATA)
        begin   
                if DATA_READY - '1' then
                        SAVE_REG <= PAR_DATA;
                        elseif CLK'EVENT and CLK = '1' then
                                SAVE_REG(1 to 7) <= SAVE_REG(2 to 8);
                        end if;
                end process;
                
                SER_OUT <= SAVE_REG(1);
                end;


I do not know how to save the code, as it does not have save option. But I considered it to be saved automatically and went to next steps:
Opened VHDL Toolbox, and set the path of the vhdl block and then try to run but in the cds.log I could see only "Loading defaults for vhdl simulator" and that's it. 
When I try to get the netlist I am getting the error and unable to get the netlist. 

Please can anyone help me out. 

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