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verilog simulation

apple419

Hi, Cadence users,

    In the process of learning Cadence...

    I created a new cell adder8 with Verilog functional view. Its symbol is also created. Now there are two views for adder8. One is functional view, and the other is symbol view.

    My question now is how do I simulate it (digitally)?

    Should I use NC-verilog? In CIW I chose tools ->  NC-verilog. The verilog environment for NC-verilog integration form appears.

    Then I filled in the Run directory, Top level design (library, cell, view), and the simulation mode (interactive), selected all three options (compile, elaborate, simulate.) 

     What is next? initialize design? generate netlist?...

    I am a beginner Cadence user. So could anyone describe the detail step by step direction? Or is there such tutorial available in this forum?

    I am using Cadence IC615. 

Thank you!

Best regards

  

Parents
  • apple419

    Hi Andrew,

       Thanks for your help. Actually I already read the help document (Virtuoso NC Verilog Environment User Guide) but I still can not get it right.

        Based on the simulation process flowchart on page 66, at the second step " Set up NC Verilog Integration for simulation", when I clicked the "initialize design" button on the left side of the window, an error pops up and says:

        ERROR (VLOGUI-18): failed to start simulation. The NC-verilog Executable field on the Simulation Setup form should not be left blank. Specify the NC-Verilog executable nama and try again.

        Then I selected setup -> simulation and opened the simulation setup form. There almost at the bottom I saw:

         NC-Verilog Executable: ncxlmode

        I did not fill the form. The content is already there when the form is opened. I guess it is the default setting?

        So the NC-Verilog executable field is not blank.

        But, is "ncxlmode" probematic?

    Best regards

    apple419 

     

     

Reply
  • apple419

    Hi Andrew,

       Thanks for your help. Actually I already read the help document (Virtuoso NC Verilog Environment User Guide) but I still can not get it right.

        Based on the simulation process flowchart on page 66, at the second step " Set up NC Verilog Integration for simulation", when I clicked the "initialize design" button on the left side of the window, an error pops up and says:

        ERROR (VLOGUI-18): failed to start simulation. The NC-verilog Executable field on the Simulation Setup form should not be left blank. Specify the NC-Verilog executable nama and try again.

        Then I selected setup -> simulation and opened the simulation setup form. There almost at the bottom I saw:

         NC-Verilog Executable: ncxlmode

        I did not fill the form. The content is already there when the form is opened. I guess it is the default setting?

        So the NC-Verilog executable field is not blank.

        But, is "ncxlmode" probematic?

    Best regards

    apple419 

     

     

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