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verilog simulation

apple419

Hi, Cadence users,

    In the process of learning Cadence...

    I created a new cell adder8 with Verilog functional view. Its symbol is also created. Now there are two views for adder8. One is functional view, and the other is symbol view.

    My question now is how do I simulate it (digitally)?

    Should I use NC-verilog? In CIW I chose tools ->  NC-verilog. The verilog environment for NC-verilog integration form appears.

    Then I filled in the Run directory, Top level design (library, cell, view), and the simulation mode (interactive), selected all three options (compile, elaborate, simulate.) 

     What is next? initialize design? generate netlist?...

    I am a beginner Cadence user. So could anyone describe the detail step by step direction? Or is there such tutorial available in this forum?

    I am using Cadence IC615. 

Thank you!

Best regards

  

Parents

  • It appears you have some wrappers installed in your environment which are taking care of running the real tools underneath. I suggest that you speak to whoever is responsible for those at your site. I've no idea what they do or how they are set up (maybe you can do "cat /home/users/can/bin/ncvlog" to see the contents of the wrapper script to see if that offers any clues.

    It seems that there's no wrapper been created for ncxlmode.

    Regards,

    Andrew.

     

Reply

  • It appears you have some wrappers installed in your environment which are taking care of running the real tools underneath. I suggest that you speak to whoever is responsible for those at your site. I've no idea what they do or how they are set up (maybe you can do "cat /home/users/can/bin/ncvlog" to see the contents of the wrapper script to see if that offers any clues.

    It seems that there's no wrapper been created for ncxlmode.

    Regards,

    Andrew.

     

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