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Simulating an imported VHDL

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Hi everybody
I'm newbie in using Cadence, so pleas forgive me if my question is too banal.
I need to simulate, using Analog Environment, a logic component (so far it's synthetized only in VHDL) which must control an analog circuit (whose schematic is created by Virtuoso tool). To do this I've imported a VHDL file into a library of Cadence, and it created the 3 views (entity, structural, symbol). (CIW -> File -> Import -> VHDL)
I put an instance of it in the Virtuoso schematic I want to simulate by the Analog Environment, but when I start the netlist and simulation, I receive the following error message:
Netlister: unable to descend into any of the views defined in the view list "spectre cmos_sch cmos.sch schematic veriloga ahdl" for instance ...

If I've uderstood, I must put in the view list in the Environment window another view, for simulating VHDL imprted, but I have no idea about which view I have to put in...
Thanks in advance
Paolo


Originally posted in cdnusers.org by Delfo
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    Paolo,

    You didn't say which simulator you're trying to use, but from the view list, my guess is that it is spectre.

    If spectre, you will need a view which is netlistable - for example, a schematic or extracted type view. If it is just VHDL language, you can't simulate that in spectre.

    When doing File->Import->VHDL, you have the ability to import structural VHDL as "schematic" - did you do that? If you open the structural view that you imported, is it a schematic, or is it textual? If it is a schematic, you should be able to put "structural" in the view list. If it is textual, it's probable that the code is not really structural...

    If you were using "ams" as the simulator (AMS Designer), then you should be able to simulate it with the language code.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • archive

    Paolo,

    You didn't say which simulator you're trying to use, but from the view list, my guess is that it is spectre.

    If spectre, you will need a view which is netlistable - for example, a schematic or extracted type view. If it is just VHDL language, you can't simulate that in spectre.

    When doing File->Import->VHDL, you have the ability to import structural VHDL as "schematic" - did you do that? If you open the structural view that you imported, is it a schematic, or is it textual? If it is a schematic, you should be able to put "structural" in the view list. If it is textual, it's probable that the code is not really structural...

    If you were using "ams" as the simulator (AMS Designer), then you should be able to simulate it with the language code.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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