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Simulating an imported VHDL

archive
archive over 19 years ago

Hi everybody
I'm newbie in using Cadence, so pleas forgive me if my question is too banal.
I need to simulate, using Analog Environment, a logic component (so far it's synthetized only in VHDL) which must control an analog circuit (whose schematic is created by Virtuoso tool). To do this I've imported a VHDL file into a library of Cadence, and it created the 3 views (entity, structural, symbol). (CIW -> File -> Import -> VHDL)
I put an instance of it in the Virtuoso schematic I want to simulate by the Analog Environment, but when I start the netlist and simulation, I receive the following error message:
Netlister: unable to descend into any of the views defined in the view list "spectre cmos_sch cmos.sch schematic veriloga ahdl" for instance ...

If I've uderstood, I must put in the view list in the Environment window another view, for simulating VHDL imprted, but I have no idea about which view I have to put in...
Thanks in advance
Paolo


Originally posted in cdnusers.org by Delfo
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  • archive
    archive over 19 years ago

    Yes, I'm using Spectre.
    I've already tried by importing the VHDL as Schematic, but it creates , together with the symbol view, an entity and a behavioral view, and both are textual. And anyway, it continues to show the same error message when I try to simulate.
    Otherwise, is there an easy way to import a logic circuit, synthetized by vhdl (just an ideal logic, at this stage I don't care about delays and power consumption), into an analog circuit and simulate all by Spectre?
    Thanks again.
    Paolo


    Originally posted in cdnusers.org by Delfo
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  • archive
    archive over 19 years ago

    Yes, I'm using Spectre.
    I've already tried by importing the VHDL as Schematic, but it creates , together with the symbol view, an entity and a behavioral view, and both are textual. And anyway, it continues to show the same error message when I try to simulate.
    Otherwise, is there an easy way to import a logic circuit, synthetized by vhdl (just an ideal logic, at this stage I don't care about delays and power consumption), into an analog circuit and simulate all by Spectre?
    Thanks again.
    Paolo


    Originally posted in cdnusers.org by Delfo
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