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How to use vcvsp with multiple inputs

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I am trying to use a vcvsp component in analoglib with multiple controlling voltages, which means the output voltage (only one output) is a function of four input voltages.  Does any one know how to use vcvsp for this kind of purpose and what kind of format of the data file should I have?  Thanks a lot.


Originally posted in cdnusers.org by dqiao

  • Hi There

    Currently VCVS doesn't support PWL file for multiple input. The common usage for multiple inputs is for digital gate modeling (type=and|nand|or|nor). You can get multiple input sources by connecting voltage sources in series or current sources in parallel. If you want to use multiple inputs, the workaround would be using 4vcvs with PWL in parallel.

    Another option can be to use $table_model function in Verilog-A which can interpret files of that format. More information on Verilog-A can be found in Verilog-A user guide in Cadence Documentation.

    Hope this information helps.


    Originally posted in cdnusers.org by chhabra

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