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verilogA timestep dynamic management

Fabb

Hello,

I am developping a verilogA module with an agressive transition on a specific current (transition occure at Ith).

To improve the accuracy I would like to reduce time step close to it.

Using  $bound_step(10p) should work, but it is for the complete simulation set, so I would prefer to dynamicazlly reduce time step only close to the transition.

For this I try

    @(cross(I-Ith,0,1p,1p))    $discontinuity (0),

and I monitor the time step with

     $display("\n--t=%r",$abstime);

I am not able to to see the impact of (cross and discontinuity statment) on the time step.

Is it normal ?

regards

fab

Parents

  • Fab,

    You can call $bound_step with a varying argument - so you could adaptively adjust the value of $bound_step during the simulation. Such a technique is commonly used in VCO models to ensure a sufficient number of points per period. You should call $bound_step on each timestep, but you could conditionally alter the variable you're passing to it.

    The $discontinuity is just a hint to the simulator to tell it how to cope - it will already force a timestep at (or close to) the threshold crossing - but it will not necessarily force it to zoom in and keep the timesteps short.

    It's not obvious what you're trying to do - maybe showing more of your model would help?

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    Can you please share the VCO model (verilog-A code) that you referred to above.

    I was looking for an accurate yet fast VCO model, this might be the solution I need.

    Thanks,

    Aman  

Reply Children
  • in reply to apskohli

    Dear apskohli,

    apskohli said:

    Can you please share the VCO model (verilog-A code) that you referred to above.

    I was looking for an accurate yet fast VCO model, this might be the solution I need.

    Have you seen the verilogA model provided by Ken Kundert at URL:

    http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

    There are two verilogA based VCO models included in the paper that might be of interest to you.  The model you are referring to, per my understanding of this very old post, is from community member Fabb.  I am sure many others exist, but don't know the extent of your specific need(s).

    Other forum members, I am sure, will have other suggestions for verilogA based VCO models as they are pervasive in my experience.

    Shawn

  • in reply to ShawnLogan

    In addition to the model pointed to by Shawn, there's also a couple of vco models shipped with the IC release, in ahdlLib and bmslib which you can access by adding:

    DEFINE ahdlLib $(inst_root_with:tools/dfII/bin/virtuoso)/tools/dfII/samples/artist/ahdlLib
    DEFINE bmslib $(inst_root_with:tools/dfII/bin/virtuoso)/tools/dfII/samples/artist/bmslib

    to your cds.lib

    Andrew 

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