Error while netlisting in UltrasimVerilog

Dear all,

I'm doing PLL top level simulations using UltrasimVerilog simulator.
I'm getting the following error while generating the netlist using ADE.

***************************************************************************************************************************
*USRERR: PseudoTerminal [@vsub:%:not_used], of instance I0 (referring to placed master dpll_sv92ex_ver_1_0.PLLCSDMS1T12.symbol), residing in cellview (dpll_sv92ex_ver_1_0.PLLCSDMS1T12_test.schematic, using configViewString verilog schematic spectre cmos_sch cmos.sch veriloga ahdl)
with inherited connection expression [@vsub:%:not_used]
is connecting to default net not_used
that is NOT A GLOBAL net.
*Error* Failed to partition the design.
      ...unsuccessful.
*Error*Unable to display raw netlist files.
****************************************************************************************************************************


Could you please let me know the way to rectify it?