Dynamic parameter and verilogA code

Hello

  I have a VerilogA block which reads in single binary bits from a file, on rising edges of an incoming clock (generated by VPULSE).

 I created a simple file where I have tscale and tscale_value and time and period values.

The 'period' parameter, incidentally, changes the period of the incoming clock.

 I can simulate and I clearly see the period of the spectre VPULSE clock change by a factor 10 as desired.

Yet the output of my VerilogA fails to output anything after this change in period.  My VerilogA block doesn't take this 'period' variable, and consists of the following after (parameter, real, pin declarations (electrical))

analog begin

@(initial_step)
fid=$fopen(type,"r");

 @ (cross( V(Mclk) - vtrans_clk, +1 ))
 begin

 $fscanf(fid,"%d",int_cs[0]);
 end

vout_val = int_cs[0] * vdd;

V(cs0) <+ 1*transition(vout_val, tdel, trise, tfall);
end

endmodule  

Does anyone know whether changing the clock period (by a factor 10), without changing reltol would result in a lack of output from the verilogA block, yet the incoming clock changes correctly. I've tried changing the clock by multiplying and dividing by 10 from the initial period, but to no avail.

K