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Test Bench for Clocked Comparator

ksnf3000
Hi All,

I have a clocked comparator. The differential stage in the design has a clock which allows it control the pMOS and nMOS transistors.

The problem i am having is while doing the dc and ac simulations of the comparator. On giving a pulse input to the Vclk pin, i am not getting the desired result.

Please let me know how the test bench should be for determining the dc and ac parameters of this circuit.

Thanks,
Kashif
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