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Test Bench for Clocked Comparator

ksnf3000
Hi All,

I have a clocked comparator. The differential stage in the design has a clock which allows it control the pMOS and nMOS transistors.

The problem i am having is while doing the dc and ac simulations of the comparator. On giving a pulse input to the Vclk pin, i am not getting the desired result.

Please let me know how the test bench should be for determining the dc and ac parameters of this circuit.

Thanks,
Kashif
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  • Andrew Beckett

    Kashif,

    Not sure your last response is terribly helpful (nor was the question from VKhlyupin to be honest).

    Anyway, you can only use ac analysis on a Linear Time Invariant system - but what you have here is a Linear Time Variant (or Linear Time Varying) system. Put another way, the ac analysis does a small signal analysis around a single dc point - but in this case your operating point is actually a period of the clock. So similarly dc doesn't make a whole lot of sense either.

    What you need to do is to use pss and pac to analysis your system. This allows you to look at the time-averaged AC response of the circuit over a period of operation. Whilst these analyses are commonly used in RF design, they are also suitable for other kinds of switching circuits such as switched capacitor filters, chopper-stabilized amplifiers, and switched comparators. See this paper for details on using it with switched capacitor design, for example.

    Kind Regards,

    Andrew.

  • VRaviteja
    in reply to Andrew Beckett

    How to make ideal clocked comparator in cadence?

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  • VRaviteja
    in reply to Andrew Beckett

    How to make ideal clocked comparator in cadence?

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