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Accumulation mode MOS accuracy?

FormerMember
FormerMember

Hello everybody, I'm Giovanni and I'm new to this forum.

 

I'm writing my master thesis and I'm using Virtuoso IC6.1.4.500.12 for simulations with tech file AMS 0.18 h18a6 . Analog Options are set as follow: reltol  = 100e-6, vabstol = 1e-6, iabstol = 1e-18, gmin = 1e-14


Since I'm simulating analog ultra low currents (atto Ampere) circuits and I'm wondering how precise the results are and if simulator models are accurate enough even for such low currents. (The model used by AMS tech should be the PSP model. However not really sure about it).

This doubt came up while I tried to compare actual measurements found in an article [1] with simulations done by myself. In fact, see attached figure, fig (b) obtained from actual measurements remarkably differs from fig (c) obtained via simulations.

In the article from which fig (b) is taken [1], the authors claims that the exponential behavuiour is due to accumulation mode source to drain coupling. 

Simulations are done with a nfethvt W = L = 1.5u. Vb = 0, Vgb = -1, Vsb = -50mV to +250mV parametrized with Vdb = 150mV to 300mV as explained in the article.

But since these two plots are qualitative very different (no exponential realtion Id vs Vsb), I'm guessing cadence doesn't model accurately the MOS for very low currents. Right?

 

Hence my question is: how trustful are cadence MOS models? Can I improve those?

(maybe setting some model parameters as done in [2])

 

Many thanks to evereybody will help me!

 

Giovanni

 

[1]   M. O’Halloran and R. Sarpeshkar, "A 10-nW 12-bit Accurate Analog Storage Cell With 10-aA Leackage," IEEE journal of solid-state circuits, vol. 39, no. 11, November 2004.

 

[2] http://www.ini.unizh.ch/~tobi/anaprose/recep/TobiElement_SPICE_Simulation.pdf




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Parents

  • The first thing would be to contact the foundry. You need to find out whether they have even characterized the model under such conditions. The most important factor is how the characterization has been done - this is setting of the device model parameters to match the measured values - and unless that has been carefully fitted in the region you're measuring, it's quite possible that the results will not be as accurate as you need - this is not necessarily a matter of how "Cadence" models the transistor - we implement the device model equations, but the foundry does the model fitting.

    I can't say for certain whether the actual device model can be accurate in such conditions or is physical - that would depend on which particular model is being used by the foundry - and even then it would be best for the foundry to work with us to check that out.

    Regards,

    Andrew.

Reply

  • The first thing would be to contact the foundry. You need to find out whether they have even characterized the model under such conditions. The most important factor is how the characterization has been done - this is setting of the device model parameters to match the measured values - and unless that has been carefully fitted in the region you're measuring, it's quite possible that the results will not be as accurate as you need - this is not necessarily a matter of how "Cadence" models the transistor - we implement the device model equations, but the foundry does the model fitting.

    I can't say for certain whether the actual device model can be accurate in such conditions or is physical - that would depend on which particular model is being used by the foundry - and even then it would be best for the foundry to work with us to check that out.

    Regards,

    Andrew.

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