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Including subcircuit netlist for hspiceD

Shep77

Hi, I am attempting to include a netlist for a subcircuit, and I am using hspiceD as my simulator/netlister. I have tried a couple of methods, and nothing seems to quite get me all the way. (FYI, I am using IC6.1.4.500.10) I have been reading the Virtuoso ADE L User's Guide section: Referencing Textual Subcircuits or Models.

  1. I have created a config view for a testbench circuit, and for the subcircuit I am trying to include, I havechanged the cellview to "Set cell view -> Source File..." and picked my netlist.
  2. If I try to netlist the circuit from here, several things get reported:
    INFO (OSSHNL-384): Valid sourcefile 'PLL_PFD.netlist' on cell PLL_PFD in config 'TB_PLL_PFD/config'. This cell will be

    treated as a stop point.

    Before I added CDF simulation information I was getting an error about no cell information. Some colleagues of mine, who are running on a different server, did not get this error (but they are running I6.1.5, maybe a fix for this has been deployed?)

  3. Now, I have gone into the Edit CDF dialog, set it to "Base", and selected my library and Cell name. under the hspiceD simulation, I have populated:
    componentName: PLL_PFD
    namePrefix: x
    termOrder: dclock data VDD VSS down up
    termMapping: nil dclock \,dclock data \,data VDD \,VDD VSS \,VSS down \,down up \,up
    I have tried leaving netlistProcedure blank and using hspiceDCompPrim with no difference in results. (I hit "Apply"!)

  4. I opened my subcircuit symbol and saved it as a hspiceD view.

Anyway, I am getting it netlisted, and it is including the netlist file, but it is not putting any pins on the subcircuit definition. What am I missing?

 Thanks,

Paul

  • Okay, I was able to fix this by adding the model CDF data as described here:
    http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade.aspx

    Happily, it does work for me to point the config file to the schematic or netlist, which I was worried about when I started on this.

    Wondering why this seems to behave differently in  IC 6.1.4 vs 6.1.5... I will admit I haven't looked to deeply into what is happening on my colleagues machine, but find it strange that their cells do not require this CDF data. Has therebeen a change in the way the Hierarchy Editor and Netlister interact on this front?

     

    Thanks!
    Paul

  • Final update for anyone out there keeping up... IC6.1.4 does none of the steps I posted previously. Therefore you must do them yourself...

    In IC6.1.5, there has been a partial implementation of automatic CDF data generation based on changes in the hierarchy editor. This is not complete! You should still go through the steps described above, and confirm that everything is correct and complete.

    In IC6.1.4, my testbench schematics which included the parasitic-extracted netlist would not netlist before the fix. However, in 6.1.5 the schematics would netlist and simulate. The scary thing was that simple digital cells would sink ~3 amps INTO VDD and the output was floating around mid-rail, suggesting that our Parasitic Extracted layouts had a major problem (of course they did not, it was really a netlisting/simulation problem). Anyway, just another lesson that, if something seems weird, you need to be able to check the entire tool flow, and understand your netlists!!!

    Thanks, Paul

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