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Mismatch simulation in Spectre

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Dear all,

I'm simulating a frequency divider circuit and the criticallity of design is the output duty-cycle. While simulating with Spectre without any pMOS/nMOS mismatch at cross-corners I'm getting a duty-cycle of 49% to 51%. However, at silicon the duty cycle obtained is ~43%.  
 
Now, I want to introduce the mismatch in pMOS/nMOS devices.  
 
Could anyone let me know how to introduce mismatch in these devices and then do the transient simulation?
 
All the help is appreciated.
 
Best Regards,


Originally posted in cdnusers.org by vj
Parents

  • Hello.

    Cadence newbie here. I have started to read the document on the designers guide website link that u posted here. However, i could not figure out the language which has been used for writing(describing) the model used..doesnt really look like spice and how does one go about entering it and/or where exactly are we supposed to enter the source file to have cadence access and use the model.

    I understand if i sound very new to cadence well thats because I am..:)...id be glad if some one cud give me some pointers to start with...

    hope to hear from you guys,

    Aijaz


    Originally posted in cdnusers.org by aijazbaig1
Reply

  • Hello.

    Cadence newbie here. I have started to read the document on the designers guide website link that u posted here. However, i could not figure out the language which has been used for writing(describing) the model used..doesnt really look like spice and how does one go about entering it and/or where exactly are we supposed to enter the source file to have cadence access and use the model.

    I understand if i sound very new to cadence well thats because I am..:)...id be glad if some one cud give me some pointers to start with...

    hope to hear from you guys,

    Aijaz


    Originally posted in cdnusers.org by aijazbaig1
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