I generated a ideal adc from model writer option and then i created symbole for that. I created a test bench for that model but when i simulate using virtuoso ADE i am getting error
The error is in my verilog module i defined as a register dout<7:0> but when i created the netlist from the schematic it is taking individual bits so it is saying that undefined model can any one help how to get single wire name in the netlist for the wide bus
i am attaching the error message and schematic with this message
What is the exact error message? Can you post the VerilogA code too?