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Have problem in simulating circuit in virtuoso ADE

sunilreddy

Hi 

I generated a ideal adc from model writer option and then i created symbole for that.  I created a test bench for that model but when i simulate using virtuoso ADE i am getting error

The error is in my verilog module i defined as a register dout<7:0> but when i created the netlist from the schematic it is taking individual bits so it is saying that undefined model can any one help how to get single wire name in the netlist for the wide bus 

i am attaching the error message and schematic with this message  

Parents

  • hai andrew

    it is verilog-AMS code

    and the error i got is same as  Problem while running verilog-ams block in cadence schematic editor started by indra

    /forums/p/26739/1325379.aspx#1325379 from that i got know that i need to setup AMS environment. i studied the user manual but i am unable to get it as i am new to linux and cadence so can you please elaborate me how to do the simulation with verilog-AMS code with schematic test bench.

     

    Regards

    Sunil  

Reply

  • hai andrew

    it is verilog-AMS code

    and the error i got is same as  Problem while running verilog-ams block in cadence schematic editor started by indra

    /forums/p/26739/1325379.aspx#1325379 from that i got know that i need to setup AMS environment. i studied the user manual but i am unable to get it as i am new to linux and cadence so can you please elaborate me how to do the simulation with verilog-AMS code with schematic test bench.

     

    Regards

    Sunil  

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