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Have problem in simulating circuit in virtuoso ADE

I generated a ideal adc from model writer option and then i created symbole for that. I created a test bench for that model but when i simulate using virtuoso ADE i am getting error

The error is in my verilog module i defined as a register dout<7:0> but when i created the netlist from the schematic it is taking individual bits so it is saying that undefined model can any one help how to get single wire name in the netlist for the wide bus

i am attaching the error message and schematic with this message

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Andrew Beckett over 12 years ago

Sunil,
I can't really give a complete tutorial here, especially when there is one in the software. Look at <ICinstDir>/doc/amsenvTutorials/amsenvTutorials.pdf
In IC5141 this is in chapter 2 of <ICinstDir>/doc/amsenvug/amsenvug.pdf
Regards,
Andrew.
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Andrew Beckett over 12 years ago

Sunil,
I can't really give a complete tutorial here, especially when there is one in the software. Look at <ICinstDir>/doc/amsenvTutorials/amsenvTutorials.pdf
In IC5141 this is in chapter 2 of <ICinstDir>/doc/amsenvug/amsenvug.pdf
Regards,
Andrew.
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