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Request help on Charge Pump Circuit

CDR78
Good Day,

Presently, I am trying to design a Charge Pump Circuit for use in PLL.

I encountered some challenges where regardless of the UP or Down pulse width variations, my Vout will always be increase and stable at 1.1V.

My understanding was that the Vout will increase when UP pulse is wider than Down pulse, while Vout decrease while Down pulse is wider than Up pulse. Vout will be stable when UP and Down pulse is equal.

Would appreciate your advice and recommendations. Thanks.

  •  Hello CDR78,

     

    without a netlist/schematic it is pretty hard  to answer such questions. I also would suggest you  to go www.designers-guide.org and see if you can get some help. The people there are more focused on design while we here focus on the tool.

     

    Kind regards,

    Marc

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