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Netlist modifies itself

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Hello, Im trying to simulate an adder circuit which produces an output depending on an 'input offset'. That is the offset gets added to itself and whenever the addition results in an overflow it should produce an output. The adder is a 4 bit adder and so whener the sum exceeds 1111 it shud produce a carry out and the resulting sum shud substract 16 from itself and produce a new sum which would then be smaller than 1111. I hope u get the point. I made schematic for the circuit which consists of a simple 4 bit Ripple carry adder and a register driven by the clock because I want the addition to take place with the clock. The output of the adder feeds the register and the reg op feeds one of the inputs to the adder thus creating a loop structure. After doing that I create a symbol out of it and use it in a TB to see the behavior. After certain simulation trials of the Test bench i get this strange error in the spectre.out file which says that "I11 instance is an instance of an undefined model subcircuit" . Here 'I11' refers to the instance name of the symbol I created earlier. This strange error disappears when i make an exact copy of the same Test Bench schematic into another schematic. And again after a while the same error pops up and then i recreate another schematic and then it works..which is becoming kind of annoying. Does anyone have any pointers as to why is it happening? Hope to get some hints about that. Best regards, Aijaz Baig.


Originally posted in cdnusers.org by aijazbaig1
Parents

  • Hello Andrew.

    Thanks for the suggestion. I tried what u said by typing the command at the ICFB window and I did see the message analog there.
    This does mean that I am indeed in the analog mode.

    Additionally when I use the simulation ->netlist recreate option I see a netlist wherein the symbol I11 in my case reads "subcircuit" instead of the name of the block which I should be seeing there.

    I thnk this is where the hierachy flattening stops and it doesnt go below that level and issues an error which is obvious as it cannot find the subblocks.

    But I do not understand what I am doing that is triggering such a strange behavior. Additionally where in the unix file structure can I find the schematic. It does show up though messed up) when I use the simulation->netlist display option bt I cannot seem to find it on the folders. Is there a way by which I can edit the schematic file manually to see if that could fix the problem.
    If I just change the name of the erroneous block from subcircuit to the name of the symbol which it represents keeping the case and everything, how do I get the netlister start the heirarchy flattening process from this point?

    Hope to hear from you guys?

    I can upload the whole library if u like..and if u have the time to look over!! :)...

    Best Regards,

    Aijaz.


    Originally posted in cdnusers.org by aijazbaig1
Reply

  • Hello Andrew.

    Thanks for the suggestion. I tried what u said by typing the command at the ICFB window and I did see the message analog there.
    This does mean that I am indeed in the analog mode.

    Additionally when I use the simulation ->netlist recreate option I see a netlist wherein the symbol I11 in my case reads "subcircuit" instead of the name of the block which I should be seeing there.

    I thnk this is where the hierachy flattening stops and it doesnt go below that level and issues an error which is obvious as it cannot find the subblocks.

    But I do not understand what I am doing that is triggering such a strange behavior. Additionally where in the unix file structure can I find the schematic. It does show up though messed up) when I use the simulation->netlist display option bt I cannot seem to find it on the folders. Is there a way by which I can edit the schematic file manually to see if that could fix the problem.
    If I just change the name of the erroneous block from subcircuit to the name of the symbol which it represents keeping the case and everything, how do I get the netlister start the heirarchy flattening process from this point?

    Hope to hear from you guys?

    I can upload the whole library if u like..and if u have the time to look over!! :)...

    Best Regards,

    Aijaz.


    Originally posted in cdnusers.org by aijazbaig1
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