I have been using Cadence Virtuoso 22.214.171.124 and the process chosen is 65nm CMOS . While trying to Layout a design it is found that the grid is not visible but if we zoom till only one transistor, the grids become visible. My querry is Is there any issue if grid is not visible while doing Layout? or if its a problem then how can I make the grid visible.
The values given in the display tab are given below
Minor Spacing: 0.01
Major Spacing : 0.05
X Snap spacing: 0.005
Y Snap Spacing: 0.005
Thanks and Regards
the visible gridpoints spacing is controlled by the "Minor Spacing" and "Major Spacing" parameter.Depending on their value they will not be displayed if you zoom out too far, there would be simply too many of them to help you in any way and they would obscure your view. So you need to increase their value till it fits your needs. I would increase the major/minor value ratio to something around 10 or higher to be usefull.
Don't play around with the x/y Snap Spacing. That's your actual drawing grid into which all your objects need to fit. If you have that wrong you will get flooded with DRC errors and the layout can't be processed by your maskshop.