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Problem in viewing grid during Layout

Jithin

Sir/Madam,

 I have been using Cadence Virtuoso 6.1.3.1 and the process chosen is 65nm CMOS .  While trying to Layout a design it is found that the grid is not visible but if we zoom till only one transistor, the grids become visible. My querry is Is there any issue if grid is not visible while doing Layout? or if its a problem then how can I make the grid visible.

The values given in the display  tab are given below

Minor Spacing: 0.01

Major Spacing : 0.05

X Snap spacing: 0.005

Y Snap Spacing: 0.005

Thanks and Regards

 Jithin K 

 

Parents
  • Sir, Even after keeping the ratio of major to minor spacing to 10, I was not able to see the grid without zooming. But when I zoom to a particular level the grid began to visible and the minor and major spacing seems to be exact as given the respective tabs. So is it because of the deep sub micron technology using I was unable to see the grid when I opened the Layout window with out any zooming. And also how should we configure the X-snap and Y-snap spacing. Thanking for your reply. Regards, Jithin K
Reply
  • Sir, Even after keeping the ratio of major to minor spacing to 10, I was not able to see the grid without zooming. But when I zoom to a particular level the grid began to visible and the minor and major spacing seems to be exact as given the respective tabs. So is it because of the deep sub micron technology using I was unable to see the grid when I opened the Layout window with out any zooming. And also how should we configure the X-snap and Y-snap spacing. Thanking for your reply. Regards, Jithin K
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