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Problem in viewing grid during Layout

Jithin

Sir/Madam,

 I have been using Cadence Virtuoso 6.1.3.1 and the process chosen is 65nm CMOS .  While trying to Layout a design it is found that the grid is not visible but if we zoom till only one transistor, the grids become visible. My querry is Is there any issue if grid is not visible while doing Layout? or if its a problem then how can I make the grid visible.

The values given in the display  tab are given below

Minor Spacing: 0.01

Major Spacing : 0.05

X Snap spacing: 0.005

Y Snap Spacing: 0.005

Thanks and Regards

 Jithin K 

 

Parents

  • Hi Jithin,

    As Marc stated, the grid value and zoom level affect whether or not the minor dots will be displayed; these should not be confused with the X and Y snap spacing values, though typically you would pick values that work together.

    Are you able to move to the IC615 release or newer since Virtuoso introduced functionality that better allows for "high altitude" editing, such as the smart snapping feature (for example the ruler can be placed and accurately snapped to edges that would otherwise require the user to zoom in).

    Regards,

    Lawrence.

Reply

  • Hi Jithin,

    As Marc stated, the grid value and zoom level affect whether or not the minor dots will be displayed; these should not be confused with the X and Y snap spacing values, though typically you would pick values that work together.

    Are you able to move to the IC615 release or newer since Virtuoso introduced functionality that better allows for "high altitude" editing, such as the smart snapping feature (for example the ruler can be placed and accurately snapped to edges that would otherwise require the user to zoom in).

    Regards,

    Lawrence.

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