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Error in Simulating Verilog XL+Analog in spectreVerilog

Hello All,

I am trying to do a simulation of a circuit which involves analog circuits,veriloga model and a verilog model. However, I am stuck with the following 2 (please see the attachment).

FYI the simulator I am using is spectreVerilog

I keep getting this error. Please let me know any way to solve this.

Thanks,

Kashif

ksnf3000 over 12 years ago

Hello All,
I am trying to do a simulation of a circuit which involves analog circuits,veriloga model and a verilog model. However, I am stuck with the following 2 (please see the attachment).
FYI the simulator I am using is spectreVerilog
I keep getting this error. Please let me know any way to solve this.
Thanks,
Kashif
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Andrew Beckett over 12 years ago

Kashif
First of all, the forum guidelines at /forums/T/19839.aspx and in each forum tell you not to post to multiple forums. So I have merged them together.
What views do you have of each of the cells? Were there any messages during netlisting? Have you checked the partitioning?
Regards,
Andrew
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