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Error in sub-range ADC simulation.

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Hello.
I am trying to simulate a 3bit ADC which incorporates sub ranging. Im using a swictched capacitor implementation of the circuit . There are 7 comparators used. these comparators are then used to select a given output of a DAC which is in actuality a thermometer code based DAC.
The circuit schematic looks like the one in my attachment.

When i try to simulate that, cadence flashes an error saying that
"Only one connection to the following 7 nodes:"
"The following branches form a loop of rigid branches (shorts) when added to the circuit:"

Why is such an error flashed? In the case of my schematic, i do actually want a connection from those 7 nodes into the negative terminal of the op-amp.
And what can be done to get rid of those errors and at the same time get that schematic implemented?

Im including a gzipped version of the relevant lib. Please do have a look if that would help you understand the error better

Best Regards,
Aijaz


Originally posted in cdnusers.org by aijazbaig1
work.tar.gz
Parents

  • The loop of rigid branches is telling you that you have a set of voltage sources in parallel (which is obviously not valid). The single connection is not an issue - it's just the loop of rigid branches.

    Having looked, it's due to the instances of the switch models (dac_switch). The ahdl views for these look badly implemented to me.

    Note, you have written these using SpectreHDL which is no longer supported - in fact in the latest versions of spectre (MMSIM61) you cannot run it at all. You should be using Verilog-A instead. SpectreHDL was a precursor to VerilogA, and is now obsolete (the syntax
    is fairly similar though, so not hard to move to).

    I didn't try to correct the model because it is not that clear to me what you're actually trying to get the switches to do (plus the fact that you'll learn more in the process of fixing it). It may just be that they need some finite impedance, but I suspect it's just that they don't represent the right relationships.

    You might want to take a look at this book: http://www.designers-guide.org/Books/#Kundert-2004 . It's an excellent book on Verilog-A and Verilog-AMS.

    Best Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Reply

  • The loop of rigid branches is telling you that you have a set of voltage sources in parallel (which is obviously not valid). The single connection is not an issue - it's just the loop of rigid branches.

    Having looked, it's due to the instances of the switch models (dac_switch). The ahdl views for these look badly implemented to me.

    Note, you have written these using SpectreHDL which is no longer supported - in fact in the latest versions of spectre (MMSIM61) you cannot run it at all. You should be using Verilog-A instead. SpectreHDL was a precursor to VerilogA, and is now obsolete (the syntax
    is fairly similar though, so not hard to move to).

    I didn't try to correct the model because it is not that clear to me what you're actually trying to get the switches to do (plus the fact that you'll learn more in the process of fixing it). It may just be that they need some finite impedance, but I suspect it's just that they don't represent the right relationships.

    You might want to take a look at this book: http://www.designers-guide.org/Books/#Kundert-2004 . It's an excellent book on Verilog-A and Verilog-AMS.

    Best Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Children
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