Error in sub-range ADC simulation.

Thanks a lot for the tip andrew.
Now that I have got the switch fixed, it does compiles properly. However, as in the case of most switched cap circuits, im having a lot of trouble with getting the circuit to converge.
I have replaced the switch with a model which does have a finite ON resistance and a big OFF resistance. Heres what the code looks like:
[code]
// $Date: 1996/10/02 00:44:13 $
// $Revision: 1.10 $
//
//
//The sample SpectreHDL library is unsupported and subject to change
//without notice. Future versions of SpectreHDL may not be compatible
//with this library.
 
//--------------------
// sw
//
// -  switch
//
// vp,vn:        output terminals [V,A]
// vctrlp,vctrln:     control terminals [V,A]
//
// INSTANCE parameters
//    vth = threshold voltage [V]
//
// MODEL parameters
//    {none}
//
// If ('vctrlp' - 'vctrln' > 'vth') then the branch between 'vp' and 'vn'
// is shorted. Otherwise the branch between 'vp' and 'vn' is opened
//

module sw(vp, vn, vctrlp, vctrln) (vth)
node [V,I] vp, vn, vctrlp, vctrln;
parameter real vth;
{
   enum {OPEN, CLOSED} sw_state;
   real Ron = 10;
   real Roff = 100M;
   
   analog {
      sw_state = (V(vctrlp,vctrln) > vth) ? CLOSED: OPEN;
    
      if ($threshold(V(vctrlp, vctrln) - vth, 1)){
//      if ($threshold(V(vctrlp, vctrln) - vth, 1, $abstol("V"), 1.0)){
           sw_state = CLOSED;
      }

      if ($threshold(V(vctrlp, vctrln) - vth, -1)){
//      if ($threshold(V(vctrlp, vctrln) - vth, -1, $abstol("V"), 1.0)){
           sw_state = OPEN;
      }

      if (sw_state == OPEN){
           V(vp,vn) <- Roff*I(vp,vn);
      }
      else{
           V(vp,vn) <- Ron*I(vp,vn);
      }
   }
}
[/code]
As u can see, i modified the code of the sw from the ahdl library. Now (supposedly) it does always have a resistance between the two terminals.

Nonetheless, I am facing convergence problems at some of the nodes and no matter what I try the warning doesn't seem to go.

Heres the schematic
And the simulation stops just after 1.25ns and it complains that the voltage/current changes at some nodes is just too much to take care of.
As suggested in some of the places and app notes, i have tried attaching a LPF kind of a structure in the hope that it may prevent a sudden change in the voltage level. I tried adding big resistors from floating nodes to ground which took care of the problem of floating nodes.
However, I do not understand how to prevent this sudden voltage change. will changing the value of ABSTOL or RELTOL make a difference. If yes then how do I do it?

Additionally, is there anything in the circuit topology which causes it besides the obvious fact that many nodes are getting connected to a single node in the netlist. The only reasonable way I could think of to solve this was to insert nominal resistances in the path so as to prevent a short between these nodes in the schematic.

As before id include the gzipped version of the relevant library. Please do have a look so you may find some factors which I may have overlooked.

Best Regards,
Aijaz

Thanks a lot for the tip andrew.
Now that I have got the switch fixed, it does compiles properly. However, as in the case of most switched cap circuits, im having a lot of trouble with getting the circuit to converge.
I have replaced the switch with a model which does have a finite ON resistance and a big OFF resistance. Heres what the code looks like:
[code]
// $Date: 1996/10/02 00:44:13 $
// $Revision: 1.10 $
//
//
//The sample SpectreHDL library is unsupported and subject to change
//without notice. Future versions of SpectreHDL may not be compatible
//with this library.
 
//--------------------
// sw
//
// -  switch
//
// vp,vn:        output terminals [V,A]
// vctrlp,vctrln:     control terminals [V,A]
//
// INSTANCE parameters
//    vth = threshold voltage [V]
//
// MODEL parameters
//    {none}
//
// If ('vctrlp' - 'vctrln' > 'vth') then the branch between 'vp' and 'vn'
// is shorted. Otherwise the branch between 'vp' and 'vn' is opened
//

module sw(vp, vn, vctrlp, vctrln) (vth)
node [V,I] vp, vn, vctrlp, vctrln;
parameter real vth;
{
   enum {OPEN, CLOSED} sw_state;
   real Ron = 10;
   real Roff = 100M;
   
   analog {
      sw_state = (V(vctrlp,vctrln) > vth) ? CLOSED: OPEN;
    
      if ($threshold(V(vctrlp, vctrln) - vth, 1)){
//      if ($threshold(V(vctrlp, vctrln) - vth, 1, $abstol("V"), 1.0)){
           sw_state = CLOSED;
      }

      if ($threshold(V(vctrlp, vctrln) - vth, -1)){
//      if ($threshold(V(vctrlp, vctrln) - vth, -1, $abstol("V"), 1.0)){
           sw_state = OPEN;
      }

      if (sw_state == OPEN){
           V(vp,vn) <- Roff*I(vp,vn);
      }
      else{
           V(vp,vn) <- Ron*I(vp,vn);
      }
   }
}
[/code]
As u can see, i modified the code of the sw from the ahdl library. Now (supposedly) it does always have a resistance between the two terminals.

Nonetheless, I am facing convergence problems at some of the nodes and no matter what I try the warning doesn't seem to go.

Heres the schematic
And the simulation stops just after 1.25ns and it complains that the voltage/current changes at some nodes is just too much to take care of.
As suggested in some of the places and app notes, i have tried attaching a LPF kind of a structure in the hope that it may prevent a sudden change in the voltage level. I tried adding big resistors from floating nodes to ground which took care of the problem of floating nodes.
However, I do not understand how to prevent this sudden voltage change. will changing the value of ABSTOL or RELTOL make a difference. If yes then how do I do it?

Additionally, is there anything in the circuit topology which causes it besides the obvious fact that many nodes are getting connected to a single node in the netlist. The only reasonable way I could think of to solve this was to insert nominal resistances in the path so as to prevent a short between these nodes in the schematic.

As before id include the gzipped version of the relevant library. Please do have a look so you may find some factors which I may have overlooked.

Best Regards,
Aijaz