Hello.I am trying to simulate a 3bit ADC which incorporates sub ranging. Im using a swictched capacitor implementation of the circuit . There are 7 comparators used. these comparators are then used to select a given output of a DAC which is in actuality a thermometer code based DAC.The circuit schematic looks like the one in my attachment.When i try to simulate that, cadence flashes an error saying that "Only one connection to the following 7 nodes:""The following branches form a loop of rigid branches (shorts) when added to the circuit:"Why is such an error flashed? In the case of my schematic, i do actually want a connection from those 7 nodes into the negative terminal of the op-amp. And what can be done to get rid of those errors and at the same time get that schematic implemented?Im including a gzipped version of the relevant lib. Please do have a look if that would help you understand the error betterBest Regards,Aijaz
Hello.I have made my way out of the strange convergent errors and what I learned in a crude way was that sudden changes in voltages and currents need to be taken care of..I basically solved that problem using buffered inputs to nodes that were floating and added high impedance resistors to ground to floating nodes for some cases. Additionally modifying the cap values also made some effect. Furthermore I changed the switch model such that there always is a path between the input and output which toggles between high imp and low imp depending on the control input.additionally the way the chassis ground (floating ground) works for an op amp has always been a little mysterious to me. How does a VCVS model that effect of the two nodes being almost equipotential.Now a question regarding to my schematic (changed). As usual im including teh schematic so that it may become easy for u to comprehend what im sayin here.when the two capacitors switch states, some charge seems to be drawn from the floating ground which causes a very sharp voltage and consequently current spike at the outputs. I learned that it depends on the difference between the present value and the value it is supposed to get charged to plus the series resistance in its path such that it shudnt have allow an infinitely large current to flow through the circuit.But how does one get rid or reduce that problem in an op amp ckt in cadence?Additionally, with regards to the circuit, that circuit seems to be implementing a transfer function of [(C_s/C_f)*(V_in - V_Ref)] + V_Ref. I wonder whats causing it to hold a value of V_Ref causing it to add an unwanted DC offset.I am keen to know if the circuit topology is affecting the behavior in anyway..im dead sure it is..bt if anyone wud give me some hints to think of..it wud be great.Best Regards,Aijaz.