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settings for Verilog Import

navi2582

Hi,

Is there a setting in the VerilogIn to include the POWER_PINS during the schematic creation?

`timescale 1ns/1ps
`celldefine
`ifdef POWER_PINS
module Std_cell_def (Y, A, B, C, VDD, VSS);
inout VDD;
inout VSS;
supply1 VDD;
supply0 VSS;
`else
module Std_cell_def (Y, A, B, C);
`endif
output Y;
input A, B, C;

  specify
    // delay parameters

    // path delays

  endspecify

endmodule
`endcelldefine

 Thanks,

  • The VerilogIn form doesn't appear to allow you to define macros although the underlying ihdl executabled does (type ihdl -help at the UNIX prompt). So either use ihdl, or you could specify a second file to import (define it first) which contains:

    `define POWER_PINS

    Probably worth contacting customer support so that we can file an enhancement CCR on your behalf to support -DEFINE from the Import Verilog form.

    Regards,

    Andrew.

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