Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 13063
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

saving verilog-a triggers compilation instead of just syntax check

danmc

 For some reason that I do not understand, when I open up a verilog-A view from the library manager, make some edits and then exit, instead of just running the normal verilog-a syntax check, it seems to want to compile the ahdlcmi stuff giving me a mylib/mycell/veriloga/veriloga.va.ahdlcmi/ directory with the compiled model in it.  I don't remember changing anything, but it just started happening and I've used verilog-A quite a bit for more than  a decade in the cadence environment.  Suggestions?

 Thanks

-Dan

 

  • Dan,

    I had a hunt around and can only find it with some old data - so I think it used to happen with an old version of MMSIM. Are you accidentally using an old MMSIM version? What version are you using? (type "spectre -W")

    Regards,

    Andrew.

  • You were on the right track Andrew.  Turns out that the environment variable we use to pick MMSIM version was set incorrectly and our deployment system then told the IC tools to use the super old spectre that was bundled with it (spectre-5).  Fixing that to point to a much more modern MMSIM made the issue go away.

     

    Thanks

    -Dan

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.