Using Virtuoso XL connectivity check

We are using IC6.1.5-64b.500.8 with a technology file we built ourselves containing the appropriate constraint groups to enable the connectivity and routing features of Virtuoso XL. We also defined a separate pin, net, and label purpose for each interconnect metal in addition to the actual drawing layer (is this the correct approach?).

When designing a single cell (logic gate), we can see how a net is gradually formed through the metal layers and vias. After the completion of the layout, we can browse through each net and see the correspondence on both the layout and schematic of the cell. This is fine. However, when instantiating the gate in a higher-level design, it seems Virtuoso XL will not recognize the nets inside the gate, only the pins (not the entire net that the pin is attached to). So when I'm conducting a design composed of instances of these cells, I must always explicity connect to the pin in order for the connectivity check to recognize there is a connection. It doesn't recognize that I made an equivalent connection if I draw a path to an equivalent net inside the gate.

This is also brings up a related issue when I attempt to draw a connection from one pin to an unrelated and internal net of a cell, it doesn't deem this as a short or incorrect connection.

*** (main point)
In otherwords, the connectivity check only appears to work at the top-level of the design. It does not take into consideration what is going on inside instantiated cells except for their pins.
***

Is this behavior by design? Do I need to place multiple pins to designate multiple options to connect to an electrically equivalent net? Or is there way to tell the tool (when working with instances of a cell) to automatically determine that this entire net is effectively a "big" pin or connecting point?

Now I've also looked into generating the abstract of the cell with the nets extracted. When viewing the abstract and scrolling through the nets, it appears the nets (in their entirety, not just the pin shape) have been extracted correctly. But I'm not sure how this information can be passed back into Virtuoso XL for connectivity checking.

Any help would be greatly appreciated. Thank you.