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  3. Verilog-A parser and HSPICE

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Verilog-A parser and HSPICE

The Setlaz
The Setlaz over 11 years ago

Hi,

 

I'm facing an issue with HSPICE ADE integration with Cadence IC5.

Basically, Synopsys forces to use their parser (hsp-vcomp) when loading their HSPICE.ile SKILL code to set HSPICE in ADE ...

Problem is their parser doesn't work ! Actually, 'hsp-vcomp' command to call Synopsys parser has been deprecated for long and is not even existing any more. It causes Verilog-A parsing to fail when closing the text-editor in Cadence environment.

 

Is there any way to force back the Verilog-A parser to Spectre (as by default)  after loading Synopsys piece of code ?

 

Thanks !

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  • The Setlaz
    The Setlaz over 11 years ago

     Hi,

     

    Just to let you know I've finally found how to revert the parser to Spectre.

    Add the following to your .cdsinit:

    envSetVal("HSPICE.envOpts" "hsp_vacompiler" 'boolean nil)

     

    And Spectre parser will be back !  May it be of any help to anyone else :-)

     

    Note: Synopsys does not seem willingful to help on this...

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  • The Setlaz
    The Setlaz over 11 years ago

     Hi,

     

    Just to let you know I've finally found how to revert the parser to Spectre.

    Add the following to your .cdsinit:

    envSetVal("HSPICE.envOpts" "hsp_vacompiler" 'boolean nil)

     

    And Spectre parser will be back !  May it be of any help to anyone else :-)

     

    Note: Synopsys does not seem willingful to help on this...

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    • Vote Up 0 Vote Down
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