LVS LAYOUT debug?!

Hello all. First, I need to let you know that this is my first layout that contains more than 2 transistors, so excuse my noobish methods. I am trying to make a 2-input xor gate. I have run DRC with no errors. I run LVS and get a couple of errors, I cannot seem to fix them, so any help will be much appreciated. I will provide screenshots for the layout and the schematic. I will also include the layout output file. In the mean time I will keep trying to fix it, if I am not able to, I think I will redo it. Thanks.

OUTPUT of LVS:

@(#)$CDS: LVS.exe version 5.1.0 06/08/2010 13:00 (cds125839) $

Command line: /ecelib/eceware/cadence04/ic5141USR6143/tools.sun4v/dfII/bin/32bit/LVS.exe -dir /users/ugrad2/2012/spring/bmasri/eecs170D/LVS -l -s -t /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/layout /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/schematic
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Compiling Diva LVS rules...

    Net-list summary for /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/layout/netlist
       count
        14              nets
        5               terminals
        6               pmos
        6               nmos

    Net-list summary for /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/schematic/netlist
       count
        6               nets
        5               terminals
        2               pmos
        2               nmos


    Terminal correspondence points
    N3        N1        gnd!
    N0        N0        vdd!

Devices in the rules but not in the netlist:
        cap nfet pfet nmos4 pmos4

    Ill-defined correspondence points.

        N0      N0  Accepted because one is a subset of the other
        N3      N1  Purged because neither is a subset of the other
        N0      N0  Accepted because one is a subset of the other
        N3      N1  Purged because neither is a subset of the other


        Device summary for layout
                   bad  total
        pmos         6      6
        nmos         6      6


        Device summary for schematic
                   bad  total
        pmos         2      2
        nmos         2      2

2 net-list ambiguities were resolved by random selection.

The net-lists failed to match.

                             layout  schematic
                                instances
        un-matched              12      4
        rewired                 0       0
        size errors             0       0
        pruned                  0       0
        active                  12      4
        total                   12      4

                                  nets
        un-matched              12      4
        merged                  0       0
        pruned                  0       0
        active                  14      6
        total                   14      6

                                terminals
        un-matched              4       4
        matched but
        different type          0       0
        total                   5       5


Probe files from /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/schematic

devbad.out:
I /P0
? Device does not cross-match.
I /P1
? Device does not cross-match.
I /N1
? Device does not cross-match.
I /N0
? Device does not cross-match.

netbad.out:
N /norIn0
? Net does not cross-match. It has 2 connections.
N /norIn1
? Net does not cross-match. It has 2 connections.
N /norOut
? Net does not cross-match. It has 2 connections.
N /gnd!
? Net does not cross-match. It has 3 connections.

mergenet.out:

termbad.out:
T -1  gnd! /gnd!
? Terminal gnd! in the schematic failed to match any terminal in the layout.
T -1  norIn0 /norIn0
? Terminal norIn0 in the schematic is not present in the layout.
T -1  norIn1 /norIn1
? Terminal norIn1 in the schematic is not present in the layout.
T -1  norOut /norOut
? Terminal norOut in the schematic is not present in the layout.

prunenet.out:

prunedev.out:

audit.out:


Probe files from /users/ugrad2/2012/spring/bmasri/eecs170D/LVS/layout

devbad.out:
The no. of lines exceeded than specified by the variable lvsLimitLinesInOutFile.
To see the complete information please see the file:
/users/ugrad2/2012/spring/bmasri/eecs170D/LVS/layout/devbad.out

netbad.out:
The no. of lines exceeded than specified by the variable lvsLimitLinesInOutFile.
To see the complete information please see the file:
/users/ugrad2/2012/spring/bmasri/eecs170D/LVS/layout/netbad.out

mergenet.out:

termbad.out:
T -1  gnd! /gnd!
? Terminal gnd! in the layout failed to match any terminal in the schematic.
T -1  xorIn0 /xorIn0
? Terminal xorIn0 in the layout is not present in the schematic.
T -1  xorIn1 /xorIn1
? Terminal xorIn1 in the layout is not present in the schematic.
T -1  xorOut /xorOut
? Terminal xorOut in the layout is not present in the schematic.

prunenet.out:

prunedev.out:

audit.out: