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Verilog import to schematics problem

Using Cadence version 6.15

The final physical verilog was produced from Encounter after successful P&R using saveNetlist -phys final.v command, but when I am using Import Verilog I get the following error:

ERROR (VERILOGIN-205): An internal memory error has occurred. Exiting.

I did not find any descriptions in logs just that error and thats it. Any ideas why?

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Kabal over 11 years ago

ok, redefining library, restarting tool helped.
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Kabal over 11 years ago

ok, redefining library, restarting tool helped.
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