Power net short error during Verilog import

I have some digital design done in Encounter, where all cells have VDD! and GND! pins, however the Global power nets are vdd and vss. The layout was done correctly, all cells have their VDD! connected to the global vdd and their GND! connected to the global vss.

However, when exported the physical verilog netlist and imported it into Virtuoso, it says something like "ERROR vdd shorted to VDD!" and "GND! shorted to vss" but thats not an error, that is what I wanted and that is how it was routed, why is it complaining on it as to an error?

Also, when I open the created schematic, I see some primitive gates with GND! and VDD! pins connected to vdd and vss lines and those pins marked with error mark "Check And Save" Operation also screams about same error.

OK, now here is a thing, I do understand that I cannot  connect two global signals. But the reason I am trying to route power for my digital module as vdd and vss is because I do not want globally defined signals in my final cell. In other words, what I want is a finished digital module with different IOs and two power pins: vdd and vss. That is why I decided to connect vdd to VDD! and vss to GND! during the encounter routing.

I tried a different approach, during Encounter routing phase define global power as VDD! and GND! and connect them appropriately to pins VDD! and GND! of each standard cell. Then after all done, save verilog physical netlist. The process went smooth then, but at the end my digital module to be used in Virtuoso will have VDD! and GND! for power pins. I could of course then us CDS_THRU primitive to make it through LVS right?

I am not sure if my last "workaround" seems good then? Is it a good idea in general to route your digital circuit with power lines defined as GND! and VDD! and then when importing it into Virtuoso just use cds_thru to connect to your global design power/frame power ring?