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Tip of the Week: Easily program digital bus values for analog sims

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There exists in the "bmslib" library a Veriloga test block that takes any decimal value and loads a digital bus with the binary equivalent.  Very useful for setting the value of digital buses for simulation. 
 
The component is called "busset8" (for the 8-bit version) or "busset4" (a 4-bit version), but one nice feature is that you can easily copy it and create any arbitrary bus size simply by changing the pin on the symbol, and changing the "NUMBITS" variable inside the Veriloga.  Even a non-Veriloga writer like myself can easily do it.
 
As an example of its use, if you wanted to set an 8-bit bus to 00001001, you would program the "setval" parameter on the symbol to "9".  (NOTE - you must set the "Tools Filter" radial button to "veriloga" to see the setval parameter to edit it.)  The output high and low levels are programmable.  The setval can also be set to a simulation parameter so that you can easily modify it in your Artist State setups.

These components also have Verilog-AMS views (which are similarly easy to modify) if you are running AMS instead of Spectre.
 
- Hugh


Originally posted in cdnusers.org by Hugh
Parents

  • You are right - I guess I assumed that copying and renaming the cell (hopefully to a library under your own control!) went without saying, but I should have included that step.

    Regarding whether (or how) you would change the setval during simulation, I can not think of how you would be able to do that with the cell as it is.  Of course, you could use a couple of them, set to different values, and then analog switches to toggle between, but that's a bit messy.  I think ideally a knowledgable Veriloga writer (which I am not) would probably be better off building a version of this cell that takes a voltage input as the "setval" parameter.  Then, a vpwl or vpulse could be used to dynamically change the setval property. 

    - Hugh


    Originally posted in cdnusers.org by Hugh
Reply

  • You are right - I guess I assumed that copying and renaming the cell (hopefully to a library under your own control!) went without saying, but I should have included that step.

    Regarding whether (or how) you would change the setval during simulation, I can not think of how you would be able to do that with the cell as it is.  Of course, you could use a couple of them, set to different values, and then analog switches to toggle between, but that's a bit messy.  I think ideally a knowledgable Veriloga writer (which I am not) would probably be better off building a version of this cell that takes a voltage input as the "setval" parameter.  Then, a vpwl or vpulse could be used to dynamically change the setval property. 

    - Hugh


    Originally posted in cdnusers.org by Hugh
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