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How to ignore FILL cells from Encounter in LVS Assura?

Kabal

I have imported some design in Virtuoso Layout from Encounter, which has some FILL cells: FILL1, FILL2, NWSX. When I do LVS with Assura, I want those cells to be ignored. This is very small part of the bigger problem desribed in some another thread, but beacuse this issue is kind of specific just to Assura I would like to ask about it separately in this thread so that someone who knows issues with Assura can give me idea.

I am attaching the error log of LVS, and the snapshot of settings how I make Assura ignore those cells using ignoreCell command. The problem is that at the beginning of the log it actually says that its going to ignore those cells, which is fine, but then it again throws error at the end saying that FILL1,FILL2,NWSX are not defined. Why is it doing it? Am I doing something wrong? 

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  • Hi Kabal,

    Andrew tipped me off on this and thought I might be able to help. Let me firts consider the "cell is not defined" issue...

    Now. I'm not is possesion of all the facts but you metion the physical verilog. Now what about the cell subckt descriptions? Typically these would be included as cdl. Do you have the cell subckt netlist also specified in your LVS run?

    N.B. For a sign-off LVS there is no way you can risk using ignoreCell. You may not be at tape-out stage yet, but down the line you do not want to have to fix this part of the flow when timescale pressures apply.

    Next...
    *ERROR* Device 'nfet(MOS)' on Layout is unbound to any Schematic device.
    Again this is indicitive of missing subckt descriptions. The cdls subckt will include the devices.

    As a precursor to sign-off LVS it would be possible to blakck box the std cells.This is a valid approach to speed up LVS iterations. For Assura there is often some rliance on the foundry correctly coding the LVS rules to support black box. But this may be an interim solution prior to including the subcircuits.

    Hope that helps.

    Rob.

  • in reply to RobMan

    hey RobMan,

    I know this thread is extremely old, but I'm encountering a similar issue when running the 45nm RFSOI process from GF.  I had to run the LEF flow through Innovus due to issues with it needing a special license on this process, but after completing the P&R, I exported the layout into virtuoso.  The layout looks good and I use the physical netlist export command from Innovus to get my Verilog netlist.  I then use this with my cdl net lists for the io and standard cells to generate my spice netlist to compare in virtuoso for LVS.  the cdl SUBCKT for the filler cells were not defined, so I created some simple ones that include just VDD and VSS pins and then convert the Verilog netlist into a spice netlist that references all of the cdl files.  After doing all of this, when I try to run lvs, the layout and spice netlist have the filler cells, but the layout states that it is missing the instance.  Any ideas would be helpful

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