Using IC6.1.5-64b.500.8, I have a core design that has a schematic view and when I want to create the physical view, I would like to use a physical-only instance to help create the physical view. This physical-only instance is really a fixed arrangement of pads and wires with no connectivity information but when I connect a net to it at the top-level, I would like Virtuoso XL to recognize that a net should continue to form through these physical-only instances. I guess you can say the physical-only instance is a common template to help wire-up my core design and any other variations of the core design. I expect to tweak this template once in a while if I have to shift some pads or wires for whatever reason.
The non-ideal solution is to place the physical-only instance and flatten it so when I work on the rest of the layout, Virtuoso XL can recognize the connections I'm making. It won't recognize these connections if I keep it as an instance even after I go to Options->Layout XL->Extraction and set "Extract connectivity level" to sufficiently high level. However, this works if I place a matching pin inside the physical-only instance using the same net name that I expect to use at the top-level, but this may not always be the case. It would be great if it could somehow inherit the net from the top-level when I connect/overlap a wire from the top-level.
The drawback of the flattening method is that if I want to update the physical-only instance, I need to delete all the flattened elements and re-instance the updated element... then I would have to do this for every design variation that used this physical-only instance.
Furthermore, Virtuoso XL warns me that the physical-only instance has no corresponding element on the schematic and it's right because it's merely just a bunch of wires and pads that will be used as connections. I'd just right click the instance in the Navigator panel and click Add Ignore for Check but I still would like Virtuoso to check if I accidentally made shorts/incomplete nets/etc.
Is there a better way to use physical-only instances when designing the layout of a schematic-based design in Virtuoso XL?
please open Options-LayoutXL and change the extractionlevel to 1 ( is probably 0 right now). Also switch on
"Allow off-pin hierarchical connnections" and "Verify hierarchical connections to unassigned shapes".
Now re-extract ( Connectivity - Update - Extract ). The tool is able to take care of such connectivity trough
the hierarchy without using pins. ( I am on 22.214.171.1240.17 , not sure you see these options in your .8 )
If you want to know more hit the "Help" button in the XL Options form and read the descriptions for these
extraction options. There is also a help chapter about "Connectivity Extraction from Unassigned Hierarchical Shapes",
thats what you are asking for, so it might be worth to read.
Thank you for your help, Marc.
Actually I do have the extraction level set to 5. And I do not have the options "Allow off-pin hierarchical connnections" and "Verify hierarchical connections to unassigned shapes" but based on the documentation, these options are enabled by default and I verified this using:
envGetVal("layout" "extractAllowOffPinHierConnections")envGetVal("layout" "extractVerifyHierConnectionsToUnassignedShapes")
Even forced it with:
envSetVal("layout" "extractAllowOffPinHierConnections" 'boolean t)envSetVal("layout" "extractVerifyHierConnectionsToUnassignedShapes" 'boolean t)
Yet when I do the re-extract (and I see my hierarchical physical-only instance listed among the other hierarchical instances), Virtuoso XL still does not recognize the connectivity through this pin-less instance. Perhaps I'm missing something else? I attached a screenshot of the extractor options...
Thanks for pointing out the chapter on "Connectivity Extraction from Unassigned Hierarchical Shapes"... I'll take a look at it now.
I can't say how the .8 is behaving since I don't have it here at the moment. But if the envVars are available it should work. I made a quick check with my .17 to see if it does work for me.
I created two Pins on Metal1, both named "A", the tool will show me the flightline for the uncomplete net between them. Then I create some wiring starting and ending with Metal1 ( to keep it simple :) ) and pushed that wiring into a cell with the "Make Cell" command.Now I overlap my A pins with the wiring in that cell and my flightline is gone and the tool is showing the net as complete.
Please try to repeat that simple test before you start with the more complex real example.
If it is still not working try to get a newer IC version.
Edit: Do you realy need 5 levels extracted? Be aware that the tool is chasing all the shapes through that hierarchy, which can hit your performance a lot. Only extract what you realy need.
I tried the simple test and it didn't work in IC6.1.5-64b.500.8 :(
However, it turns out we do have x.15 available and I gave that a go. Not only do I see the "Allow off-pin hierarchical connnections" and "Verify hierarchical connections to unassigned shapes" options in the extractor tab, but the simple test example works as well as my actual design example.
Thanks for your help, Marc! This is exactly the functionality I need.
Regarding the 5-level extraction... you're right I do not need 5 levels, the actual hierarchy is probably 2 or 3 levels but it's a small design and I haven't seen the tool struggle at this point. I'll keep this in mind if I run into performance issues.