how to set the voltage initial condition between two nodes?

Capacitors (at least analogLib cap) provide an "ic" parameter which allows you to do precisely this.

Regards,

Andrew.

Andrew,

    OK, I used the "ic" parameter in the AC simulation. When it is done, then I go to Results > Annotate > DC Node Voltages. The voltage shown on the cap is not the voltage I initialized. It seems showing the voltage on the cap in DC condition. Is it right?  Also when I go to Results > Annotate > DC Operating Points, it does not show any information (current, voltage) on the cap. The cap is from the "analogLib" library.

    Can initial conditions be used in AC simulation? Does it use the initial condition I put in to calculate the AC performance?

 Thanks 

Andrew,

   I tried it with a simple circuit. Put a voltage source VDC with  DC voltage = 3V and AC magnitute =1V. Then connect a diode to it. The anode of the diode connects to the VDC plus terminal. The cathode of the diode connects a 1pF cap. The other end of the cap goes to the GND. The VDC minus terminal goes to GND.

   Set the initial condition of the cap to 1V then run a AC simulation. Then change it to 2V, do AC simulation again. I don't see any difference between these two runs. Is it correct? I think it is not because with different operating points, the results should be different.

Thanks 

By default ac analysis doesn't honour initial conditions (nor does dc analysis). You have to add the parameter force=all or force=dev to the ac (or dc) analysis options.

Note that I've not tried your example - but hopefully this will help (I'm a bit pushed for time this week).

Regards,

Andrew.

Andrew,

   I tried what you suggested and it worked!

   It is different from PSPICE. Previously with PSPICE the initial condition setting applies to both transient and DC/AC case and I don't need to have to force it. Here with Cadence by default it only applies to transient.

Thanks a lot. 

 Regards,

 Apple419 

HI Andrew,

 I just try to implement Initial Condition for local PDK capacity for same CDF setting as analogLib cap, even add the parameter force=all but not working for Node Voltage. Is there any thing related to Model File?

Please advise.

Thanks,

Xinjie 

I don't think I have enough information to know what your problem is. I think we'd need to see the PDK setup and models - potentially if the device is actually a subckt model, then ic won't work on it. Can you contact customer support so that we can take a look?

Regards,

Andrew.

Hi Andrew,

Thanks for your quick response.

Actually the model is written as subckt, like:

///////////////////////////////////////////////////////////////////////////// 

inline subckt cap (A B SUB) 

parameters  ******

CAP1 (A B)  *******

CAP2 (SUB B) ****** 

**********

//////////////////////////////////////////////////////////////////////////////

 Is that means that ic would not working on it?

Thanks for your comment.

Regards,

Not unless you create a subckt parameter for the initial condition, and pass it down to the capacitor inside (presumably CAP1 is more important to set than CAP2, but you might need two initial condition parameters).

An "ic" parameter on the instance of the capacitor won't help unless it's consumed within the subckt.

Andrew.