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Timestamp.....

Hi,

Is there a way of checking timestamp to see if anything(both layout and schematic) has been checked in AFTER the top level has been

verified (drc/lvs cleaned) ??

I'm using cadence ic615.06.15.151

Thanks a lot,

Andrew Beckett over 11 years ago

Not really, at least not without writing something yourself. You're talking about "check in" so maybe this is something your design management vendor provides?
Regards,
Andrew.
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aflex over 11 years ago

I think schematic and layout editor can solve your issue. Also netlists can also help.
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