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LVS versus physical Verilog from Encounter, Power Node Mismatch

Kabal

OK, my battle over the LVS versus the physical Verilog file exported from Encounter continues. Finally, I think I kind of managed at least to get LVS working without quitting with error. i.e. it does run and completes successfully.

However, right now I have another issue, which is basically netlist mismatch.  I am going to attach two files here, a picture with a snapshot of console window from which I export physical verilog from encounter, the LVS run options window where I show how I configure LVS before run. 

 Another file, is just LVS log output, where it tells what specifically does not match. Now let me discuss this, as you see it says something like: Layout net: GND! shorts to I__13/GND!

I kind of don't get it. I mean GND! is global ground and VDD! is global power, they MUST "short" to GND! and VDD! of each cell of course. why would LVS complain?
 
On the other hand, I know that globals cant be "shorted" to globals. But that is the way it was routed in encounter.
As you know, in encounter for the power we usually put VDD! and for ground GND! and each GND! and VDD! of each cell connects to that global VDD!  and GND!.
 
What is the proper way then to do it? 
 
Or what is the proper way then to tell LVS that it is "OK" that those lines are shorting.
 
(do not suggest something like cds_thru because I am doing LVS of layout versus the physical verilog file)
 
Any ideas? 
Parents

  • Rob, thanks for reply,
    I read your other replies, and I think first problems with which Andrew also was helping out are solved. Now, its all about proper power net handling in an encounter cell in order to pass LVS and not having it complaining on power nets.

    1) I am attaching the exported physical verilog file. Let me tell you something more, the standard cells have GND! and VDD! as a pins!

     

    2)
     * I have no anything "GLOBAL" defined in standard cell CDL file

    * I am not using any cdlGlobalMode  setting 

    3) there is no  I__13 in netlist,  I__13 is an instance of "Layout" view, and there *is* of course  I__13 in the layout. That specific error basically says that GND! net should not short to that instance at all. So its mad that GND! is shorted to GND! of that instance on the first place. 

    4) So, for example, when I was doing power routing in Encounter, I selected to connect global power VDD! to VDD! of each pin, and connect global power GND! to GND! of each pin. Otherwise it wouldnt connect, if I would for example "connect global VDD! to vdd of each pin" it would say something like "theres no vdd pin in a cell", again, because cells have VDD! and GND! pins as their power pins.

     What really confusing is, as you know, it is wrong to short global to global etc, but thats the way kit comes! It has all cells with GND! and VDD! pins, and I am suspecting this is somehow makes LVS mad.

     In other words, right now, LVS completes successfully, i.e. doesnt quit with error, but it just isnt happy with those power pins. I am not sure then now, what is the most proper way to handle those power connections? 

     5) Also, you know I actually found relatively similar post on this thread:  /forums/T/3023.aspx
    But in my case situation is rather different, so, at this stage I just want to know what is the proper way to handle all those power related pins issue? 

    final.zip
Reply

  • Rob, thanks for reply,
    I read your other replies, and I think first problems with which Andrew also was helping out are solved. Now, its all about proper power net handling in an encounter cell in order to pass LVS and not having it complaining on power nets.

    1) I am attaching the exported physical verilog file. Let me tell you something more, the standard cells have GND! and VDD! as a pins!

     

    2)
     * I have no anything "GLOBAL" defined in standard cell CDL file

    * I am not using any cdlGlobalMode  setting 

    3) there is no  I__13 in netlist,  I__13 is an instance of "Layout" view, and there *is* of course  I__13 in the layout. That specific error basically says that GND! net should not short to that instance at all. So its mad that GND! is shorted to GND! of that instance on the first place. 

    4) So, for example, when I was doing power routing in Encounter, I selected to connect global power VDD! to VDD! of each pin, and connect global power GND! to GND! of each pin. Otherwise it wouldnt connect, if I would for example "connect global VDD! to vdd of each pin" it would say something like "theres no vdd pin in a cell", again, because cells have VDD! and GND! pins as their power pins.

     What really confusing is, as you know, it is wrong to short global to global etc, but thats the way kit comes! It has all cells with GND! and VDD! pins, and I am suspecting this is somehow makes LVS mad.

     In other words, right now, LVS completes successfully, i.e. doesnt quit with error, but it just isnt happy with those power pins. I am not sure then now, what is the most proper way to handle those power connections? 

     5) Also, you know I actually found relatively similar post on this thread:  /forums/T/3023.aspx
    But in my case situation is rather different, so, at this stage I just want to know what is the proper way to handle all those power related pins issue? 

    final.zip
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