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Adding Layout block from Encounter to custom design

Kabal

I managed to get Encounter auto-route and place the design, imported it into the Virtuoso environment as a Layout view, then runned DRC, then runned LVS versus the CDL file of standard cells and verilog file exported from encounter.

Now, I want to put this layout inside another custom layed out design. Right now, I have one design with some transistors, manually connected in schematic, and manually layed out, so I want to add this layout to that design and put it in a top level block, and then DRC and LVS it.

The way I do manual designs is, I first do schematics by hand in SchematicsXL, then I export the CDL netlist, then I pass it through the LVS script of IBM kit to convert it to LVS suitable format. Then I do layout, and do LVS versus the CDL netlist.

But in this case, I am going to use the layed out and separately LVS'ed Layout I have in another cell. That another cell has only Layout view, and a Symbol view I created for it.

The thing is, once I put that symbol inside a schematic with custom elements, and try to export netlist, the system complains saying that there is no "schematic" view.

In my export window of netlist as a View List there is: auCdl schematic, and as stop view: auCdl.

 My question is: How do I integrate my imported Layout block on a schematics level in my top level block with manually designed stuff around it? Because, there is no "schematic" view in that Layout block, I did its LVS versus the CDL file of standard cells lib and verilog file from encounter.

 I searched and know that people also do something like, import verilog to schematics. But then, my another question is, can I avoid that step? I really do not want to deal with schematics, even though this design is not that big, but I dont want to deal with it during the next very big designs.

Is there a way to export netlist from schematics with symbol of another imported block which only has Layout view without dealing with its schematics? 

Parents
  • Thanks for reply Andrew,

    I dont have it all working properly. Although I managed to get it to LVS. Let me describe my actions.

    1) Create custom symbol in auCdl view, which has exact pin types as Layout
    view.

    2) While auCdl view is open run this in CIW:
    artGenerateHierSymbolCDF(geGetEditCellView())

    And get this output:
    INFO (SCH-1171): Cross View Check completed with no errors.
    INFO (SCH-1181): "r_test4 refleks_switcher auCdl" saved.
    t
    artGenerateHierSymbolCDF(geGetEditCellView())
        Adding base cell CDF parameter information ...
        Adding base cell CDF simulation information ...
    t


    3) Create some top design, then as a symbol, add auCdl view of symbol created
    before, connect some top ports (I just chosen for simplicity add port "a" to
    all inputs and port "z" to all outputs), and also connect VDD! and GND! pins
    to the vdd and vss of the top instans through the "cds_thru" primitive.

    4) Export CDL netlist

    5) Pass that CDL Netlist through the preprocessor for LVS, to create final
    CDL netlist for LVS

    6) Open the final CDL netlist and just add this:
    *.RESI
     
    7) Create top layout cell, in which I instantiate the Layout view, and add top ports to it. 
     
    8) Run Assura LVS on the top layout cell, before run, as a netlist now three files are included:
    verilog file final.v for the digital design for which layout was generated
    CDL netlist of standard cells the exported CDL netlist of top cell from above steps.

    I am attaching 4files:
    a) schematic of my top cell which has top ports a and z, top power supply pins vdd and vss.
    b) The exported CDL netlist file with which I managet to get it working: netlist_final_working.txt
    c) CDL netlist file which did not work as it supposed to, and resulted in LVS pin mismatch errors: netlist_final_NOT_working.txt
    d) The snapshot of Properties->Pin Order window for auCdl view cell 
     
     First of all, I decided just to run LVS after step (8) above, it resulted in many pin mismatches.
    And I have no idea why?
     
    If you take a look at the pin order snapshot window in attached posts. And then if you take a look at the netlist_final_NOT_working.txt CDL file, you can notice that the CDL file has connections made properly in the right order, specifically, that line:
    XI7 GND! VDD! a a a a a a a a a a a a a a a a a a z z z z z z z z a /  
     
     If you again look at the schematic, you will see that a is connected to all appropriate ports, and z as well, so is vdd and vss through the cd_thru.
     
    So, why on earth wouldnt this thing run the LVS properly? What am I doing wrong?
     
    Now, if you take a look at another file, netlist_final_working.txt, which is a CDL file after final export. You will see this line:
    XI7 a a a a a a a a a a a a a a a a a a a z z z z z z z z VDD! GND! /  
     
     That line is the line  which I modified *myself*, i.e. manually. So that file has total two modifications, this mentioned line, and *.RESI added as in first file.
     
    And now, if I run LVS it works! Netlists match!
     
    I think I am kind of close to proper solution, the only thing is, I am *NOT* supposed to do such kind of modifications by hand in CDL file (!), this supposed to work as in case described above, but as you saw, it didnt.
     
    Any ideas why? 
     
     

Reply
  • Thanks for reply Andrew,

    I dont have it all working properly. Although I managed to get it to LVS. Let me describe my actions.

    1) Create custom symbol in auCdl view, which has exact pin types as Layout
    view.

    2) While auCdl view is open run this in CIW:
    artGenerateHierSymbolCDF(geGetEditCellView())

    And get this output:
    INFO (SCH-1171): Cross View Check completed with no errors.
    INFO (SCH-1181): "r_test4 refleks_switcher auCdl" saved.
    t
    artGenerateHierSymbolCDF(geGetEditCellView())
        Adding base cell CDF parameter information ...
        Adding base cell CDF simulation information ...
    t


    3) Create some top design, then as a symbol, add auCdl view of symbol created
    before, connect some top ports (I just chosen for simplicity add port "a" to
    all inputs and port "z" to all outputs), and also connect VDD! and GND! pins
    to the vdd and vss of the top instans through the "cds_thru" primitive.

    4) Export CDL netlist

    5) Pass that CDL Netlist through the preprocessor for LVS, to create final
    CDL netlist for LVS

    6) Open the final CDL netlist and just add this:
    *.RESI
     
    7) Create top layout cell, in which I instantiate the Layout view, and add top ports to it. 
     
    8) Run Assura LVS on the top layout cell, before run, as a netlist now three files are included:
    verilog file final.v for the digital design for which layout was generated
    CDL netlist of standard cells the exported CDL netlist of top cell from above steps.

    I am attaching 4files:
    a) schematic of my top cell which has top ports a and z, top power supply pins vdd and vss.
    b) The exported CDL netlist file with which I managet to get it working: netlist_final_working.txt
    c) CDL netlist file which did not work as it supposed to, and resulted in LVS pin mismatch errors: netlist_final_NOT_working.txt
    d) The snapshot of Properties->Pin Order window for auCdl view cell 
     
     First of all, I decided just to run LVS after step (8) above, it resulted in many pin mismatches.
    And I have no idea why?
     
    If you take a look at the pin order snapshot window in attached posts. And then if you take a look at the netlist_final_NOT_working.txt CDL file, you can notice that the CDL file has connections made properly in the right order, specifically, that line:
    XI7 GND! VDD! a a a a a a a a a a a a a a a a a a z z z z z z z z a /  
     
     If you again look at the schematic, you will see that a is connected to all appropriate ports, and z as well, so is vdd and vss through the cd_thru.
     
    So, why on earth wouldnt this thing run the LVS properly? What am I doing wrong?
     
    Now, if you take a look at another file, netlist_final_working.txt, which is a CDL file after final export. You will see this line:
    XI7 a a a a a a a a a a a a a a a a a a a z z z z z z z z VDD! GND! /  
     
     That line is the line  which I modified *myself*, i.e. manually. So that file has total two modifications, this mentioned line, and *.RESI added as in first file.
     
    And now, if I run LVS it works! Netlists match!
     
    I think I am kind of close to proper solution, the only thing is, I am *NOT* supposed to do such kind of modifications by hand in CDL file (!), this supposed to work as in case described above, but as you saw, it didnt.
     
    Any ideas why? 
     
     

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