This problem differentiates from another post, but it is more relevant to termOrder case, thats why I created separate this thread.The problem is that during LVS I get a lot of pin mismatches, however; according to the CDL netlist for LVS all the schematic-to-pin connection in the top cell are correct.Again, I have one cell with layout view generated before, and with a auCdl view as a symbol. So it has just two views, layout and auCdl. The name of that cell with two views is refleks_switcher. I instantiate the auCdl view of refleks_switcher cell in another top level cell called refleks_switcher_wrapper. After that, I export the CDL netlist for LVS. Then I go ahead and create another layout, that layout is basically a wrapper layout, I just instantiate refleks_switcher layout view and then add ports with "_top<N>" suffix in them, where N is just number of each individual port. Then I perform the LVS of the top layout view, and get a lot of pin mismatch errors. For example something like this:
Pin SchNet : LayNet--- ------ : ------rst pwm_ctrl_top : rst_toppwm_ctrl pwm_out_top<0> : pwm_ctrl_topThis does not make any sense! If you look at the attached CDL netlist file, you will see that the cell refleks_switcher or XI19 is connected properly pin-by-pin according to SUBCKT and PININFO statements! and same goes for layout! I have no idea why this tools acting crazy!
I am attaching 5 files in this and next posts:
cdf_properties.png - snapshot of refleks_switcher CDF properties, where you can clearly see my termOrder defined.schematic_top.png - snapshot of schematic in top cell called refleks_switcher_wrapper with the auCdl view of refleks_switcher cellrefleks_switcher_wrapper.netlist.lvs - a CDL file produced from top schematic for LVS.cdf_dump.txt - CDF dump of refleks_switcher celllvs_output.txt - an LVS output which shows pin errors.
Without seeing your verilog, it's hard to know - but it appears that the issue may be related to the order of the bus expansion. If you need to control the order, you'd have to put the individual bits in the termOrder in the right order. I think otherwise the order is form LSB to MSB - and if this doesn't match the order in the Verilog, it won't work. Looking at what you've changed, it's that the order was original 0 to 7 and is now 7 to 0.
I'm not that sure that the [ vs <> should matter here - because the leaf cell (refleks_switcher) is going to connect by order, not by name.
You confused me a bit because the original post didn't look the same when I looked at it, so I assume you edited it after posting.
BTW, you wouldn't normally instantiate an auCdl view directly in the schematic. You'd have a symbol and an auCdl view (which are the same). You instantiate the symbol, and then during netlisting it would view switch to the auCdl view. It shouldn't cause problems doing what you've done, but it's a little unusual.