This problem differentiates from another post, but it is more relevant to termOrder case, thats why I created separate this thread.The problem is that during LVS I get a lot of pin mismatches, however; according to the CDL netlist for LVS all the schematic-to-pin connection in the top cell are correct.Again, I have one cell with layout view generated before, and with a auCdl view as a symbol. So it has just two views, layout and auCdl. The name of that cell with two views is refleks_switcher. I instantiate the auCdl view of refleks_switcher cell in another top level cell called refleks_switcher_wrapper. After that, I export the CDL netlist for LVS. Then I go ahead and create another layout, that layout is basically a wrapper layout, I just instantiate refleks_switcher layout view and then add ports with "_top<N>" suffix in them, where N is just number of each individual port. Then I perform the LVS of the top layout view, and get a lot of pin mismatch errors. For example something like this:
Pin SchNet : LayNet--- ------ : ------rst pwm_ctrl_top : rst_toppwm_ctrl pwm_out_top<0> : pwm_ctrl_topThis does not make any sense! If you look at the attached CDL netlist file, you will see that the cell refleks_switcher or XI19 is connected properly pin-by-pin according to SUBCKT and PININFO statements! and same goes for layout! I have no idea why this tools acting crazy!
I am attaching 5 files in this and next posts:
cdf_properties.png - snapshot of refleks_switcher CDF properties, where you can clearly see my termOrder defined.schematic_top.png - snapshot of schematic in top cell called refleks_switcher_wrapper with the auCdl view of refleks_switcher cellrefleks_switcher_wrapper.netlist.lvs - a CDL file produced from top schematic for LVS.cdf_dump.txt - CDF dump of refleks_switcher celllvs_output.txt - an LVS output which shows pin errors.
Hi Andrew,Yes original post had simpleer example, I deleted it, then put this example where all top ports are different to better udnerstand situation.You was actually right about verilog port order, in fact I was suspecting that too before, but since it didnt matter because of [ <> issues I thought its not verilog order which matters. Only when I managed to get it working after changing <> to [ during netlisting and after arranging my ports in CDF termOrder I discovered now that they match the way how they appear in verilog!Here is the description of top instance from verilog:
module refleks_switcher ( clk, rst, pwm_in_port1, pwm_in_port2, pwm_ctrl, pwm_out, \VDD! , \GND! );If you look again at the working final netlist from my previous post, you will see that it matches the verilog port order shown above!So, turns out, that in order to get it working, one just needs to create auCdl and symbol views which are same, go to CDF properties and arrange the termOrder in a way in which it appears in the top verilog cell in verilog source.Then in LVS, just put in three files: top verilog source, CDL description of standard cells and final CDL netlisting of top structure.And yes, <> vs [ matters! I verified it! If I do not use an option to change <> to [ during netlisting the LVS goes banana. The only weird downside is, as I described before, after Netlisting with <> to [ change option, the exclamation mark "!" is removed after all GND and VDD ports, so I have to go ahead and add them, but its kinda ok, I can live with it so far, at least things are working as they "supposed" to.p.s. also had to add *.RESI to final netlist because of those cds_thru things. And yes, I will use auCdl and symbol views which have same content from now on. Also, I control CDF bus ordering with "D" property set up in .simrc.OK, finally, digital placing/autorouting with further integration in Virtuoso without involving schematics is achieved.Thanks.